tag: power optimization

Cars, Security, And HW-SW Co-Design
By Jeff Dorsch - 31 Aug, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

Accuracy Is Relative
By Ann Mutschler - 11 Aug, 2016 - Comments: 0

I've been doing some thinking on the concept of accuracy lately in my article, Does Power Analysis Need To Be Accurate? And, I’ve come to the conclusion that there isn’t a single conclusion to be had. Accuracy is very relative to the task at hand, as well as the use case, and the very specific power requirements. And maybe the focus shouldn't be always on the accuracy, but on what the chan... » read more

Does Power Analysis Need To Be Accurate?
By Ann Mutschler - 11 Aug, 2016 - Comments: 1

The mere mention of accuracy in power analysis and optimization today can trigger a contentious discussion, even among typically reserved engineers. What is needed and where? Which tools are truly as accurate as claimed? And how much accuracy is actually needed for power analysis, [getkc id="112" kc_name="estimation"], and optimization? First of all, the accuracy required really depends o... » read more

Powerful New Standard
By Brian Bailey - 02 Mar, 2016 - Comments: 1

In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

Micro-Architectural Exploration For Low Power Design
By Abhishek Ranjan - 10 Dec, 2015 - Comments: 0

By Abhishek Ranjan, Saurabh Shrimal and Sanjiv Narayan In the first part of this series, we discussed the need to perform power optimizations and exploration at higher levels of abstractions, where the potential to reduce the power consumption was highest. While fine-grained local changes (like clock-gating, operand isolation, etc.) for power reduction are well understood and widely adopted,... » read more

Micro-Architectural Exploration For Low Power Design
By Abhishek Ranjan - 12 Nov, 2015 - Comments: 0

By Abishek Ranjan, Saurabh Shrimal and Sanjiv Narayan The adoption of finFET technology has created a tectonic shift in the chip design landscape. In addition to better performance (within the same power envelope) and higher reliability, finFETs have significantly reduced the leakage power at smaller technology nodes. At the same time, the share of dynamic power dissipation continues to rise... » read more

Formal Low-Power Verification Of Power-Aware Designs
By Cadence - 15 Jun, 2015 - Comments: 0

Power reduction and management methods are now all pervasive in system- on-chip (SoC) designs. They are used in SoCs targeted at power-critical applications ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Power reduction methods are now applied throughout the chip design flow from architectural design th... » read more

A Survey Of Our Low Power Blogs In 2014
By Rob Eccles - 12 Dec, 2014 - Comments: 0

Over the past year, we have written a number of blogs on low power IC design. Here at the end of 2014 approaches, let’s look back at what we have discussed Our blogs covered methods to estimate and reduce power consumption in digital ICs. Our recommendation is that you do this early in the design cycle, such as the RTL coding stage, when you can have the most positive impact. In the first... » read more

Memory Gating Power Optimizations
By Rob Eccles - 07 Nov, 2014 - Comments: 0

Saving power in SOCs is challenging. Often there are many memories, which collectively can consume a significant amount of power, compelling designers to make architectural choices to minimize power. These require a fair amount of study and may impact functionality and/or embedded software. Fortunately, memory gating can save power without impacting the architecture or the software. The... » read more

Power Exploration: MLB World Series, Bumgarner, And Box Scores
By Mark Baker - 06 Nov, 2014 - Comments: 0

The San Francisco Giants are fresh off their third Major League Baseball (MLB) World Series win in the last 5 years. That's notable in itself, but then consider Madison Bumgarner, the starting pitcher for the Giants who was named the 2014 World Series MVP. Bumgarner finished this year’s series with a 2-0 record, one five-inning save (game seven) and 0.43 ERA in three appearances, highlighting... » read more

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