The Growing Software Challenge: From Stacks To SMP


By Ann Steffora Mutschler Building a system now includes software, but defining the software stack is a mounting challenge for engineers. What used to be almost exclusively drivers now includes RTOSes and OSes, executable files, middleware, firmware, IP, embedded software and applications. With millions of different embedded products, all with different sets of software, it comes down to pr... » read more

The Upside Of Glitches


There has always been a struggle between the verification and marketing sides of any chip company. The solution in the past has simply been to hire lots more verification engineers on a contract basis prior to tapeout and to muscle through the debug process. Creating a more generic platform and differentiating it with software changes that equation, and that is raising lots of concern behind... » read more

Redefining ‘Good Enough’


The increasing amount of software content in devices and the ability to add fixes after tapeout is changing the definition of what’s considered a market-ready product. This is business as usual in the software world, where patches upon patches are considered routine. Service packs are a way of fixing problems when millions of lines of code interact with millions more lines of code in unan... » read more

Experts At The Table: Verification Nightmares


By Ed Sperling Low-Power Engineering sat down with Shabtay Matalon, ESL marketing manager in Mentor Graphics’ Design Creation Division; Bill Neifert, CTO at Carbon Design Systems; Terrill Moore, CEO of MCCI Corp., and Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. What follows are excerpts of that conversation. LPE: How important is a high-leve... » read more

New Math: 1+1=1?


From the standpoint of place and route, synthesis, and even some pieces of the hardware verification, the cost of chips even at advanced nodes hasn’t budged. It’s now possible to create a chip at 28nm with roughly the same budget as a 40nm chip, and inside many companies that’s what the hardware engineering manager sees. Look across the entire SoC design chain, however, and the picture... » read more

What Went Wrong At Toyota?


There’s been a lot of speculation about what caused Toyotas in general, and the Prius in particular, to suddenly accelerate. All across the electronics industry, this is big news because of the amount of electronics that now sits inside an automobile. The most advanced cars have complicated networks of processors, memory, logic, and basically everything that’s already built into the most... » read more

How Accurate Is Software?


The number of corner cases is growing. In hardware, that means more verification, more testing and more re-spins. But in software there is no comparable verification method. The Prius braking problem was blamed on a software glitch, but as Synopsys CEO Aart de Geus succinctly noted, none of Toyota’s rivals rushed out to trumpet their own software methodologies. While software adds flexib... » read more

The Bigger Picture


The pace of change in system-level design is no longer confined just to technology. It now hinges largely on whether enough engineers can make the leap from RTL or synthesis or verification or any other specialty to systems engineer. This is no small feat. It requires re-tooling and learning of modeling and other concepts that until now have been largely at the architectural level. It may ... » read more

Software Becomes The Main Differentiating Factor


By Ed Sperling Software has always been critical in determining what makes one chip different from another, but for the next couple of process nodes it will take on new significance. Rather than just defining function, it also will be one of the key determinants in performance and function. Behind this change is a bottleneck in lithography, which generally is not something most design eng... » read more

Writing Software For Low-Power Systems


By Ed Sperling Almost any discussion of software in low power systems these days involves some sort of multicore approach. That is particularly true at 90nm and below. At 65nm, unless there is a very distinct purpose for a low-power single-core device, it probably is utilizing at least two cores, and at 45nm the numbers can continue to rise, depending upon how many functions the chip is being... » read more

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