tag: Synopsys

Blog Review: Aug. 9
By Jesse Allen - 09 Aug, 2017 - Comments: 0

Cadence's Paul McLellan digs into a recently discovered vulnerability in the Broadcom Wi-Fi chip used in many smartphones and why it should be a wakeup call for SoC designers. Mentor's Craig Armenti considers whether work-in-process design data management is an asset or a liability. Synopsys' Thomas M. Tuerke notes that in code, as in medicine, proper hygiene is should be treated as a con... » read more

The Rising Value Of Data
By Ed Sperling - 09 Aug, 2017 - Comments: 0

The volume of data being generated by a spectrum of devices continues to skyrocket. Now the question is what can be done with that data. By Cisco's estimates, traffic on the Internet will be 3.3 zetabytes per year by 2021, up from 1.2 zetabytes in 2016. And if that isn't enough, the flow of data isn't consistent. Traffic on the busiest 60-minute period in a day increased 51% in 2016, compare... » read more

The Week In Review: Design
By Jesse Allen - 04 Aug, 2017 - Comments: 0

M&A Invecas will acquire Lattice Semiconductor's HDMI design team and Simplay Labs subsidiary, which oversees standards compliance and interoperability testing services. Invecas supplies foundation, analog, and interface IP optimized for GlobalFoundries processes. The deal is expected to close later this month. Last year, Lattice announced it would be acquired by Chinese private equity fir... » read more

IP Business Changing As Markets Shift
By Ed Sperling - 03 Aug, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IP protection, tracking and reuse with Srinath Anantharaman, CEO of [getentity id="22203" e_name="ClioSoft"]; and Jeff Galloway, CTO of Silicon Creations; Marc Greenberg, group director of product marketing for [getentity id="22032" e_name="Cadence"]'s IP Group; and John Koeter, vice president of marketing for [getentity id="22035" e_name="Synopsys"... » read more

Using Machine Learning In EDA
By Ann Mutschler - 02 Aug, 2017 - Comments: 0

Machine learning is beginning to have an impact on the EDA tools business, cutting the cost of designs by allowing tools to suggest solutions to common problems that would take design teams weeks or even months to work through. This reduces the cost of designs. It also potentially expands the market for EDA tools, opening the door to even new design starts and more chips from more compan... » read more

Blog Review: Aug. 2
By Jesse Allen - 02 Aug, 2017 - Comments: 0

In a video, Cadence's Marc Greenberg describes the post-package repair capability in LPDDR4 and why it's important for future LP/DDR5 memories. Synopsys' Kiran Vittal looks at formal, machine learning, and when computers beat humans at games. Mentor's Matt Knowles digs into how cell-aware diagnosis works and why it can find tricky finFET defects. ARM's Freddi Jeffries digs into why com... » read more

CCIX Enables Machine Learning
By Brian Bailey - 31 Jul, 2017 - Comments: 5

It takes a lot of technology to enable something like machine learning, and not all of it is as glamorous as neural network architectures and algorithms. Several levels below that is the actual hardware on which these run, and that brings us into the even less sexy world of interfaces. One such interface, the Cache Coherent Interconnect for Accelerators (CCIX), pronounced C6, aims to make th... » read more

The Week In Review: Design
By Jesse Allen - 28 Jul, 2017 - Comments: 0

IP Synopsys unveiled High Bandwidth Memory 2 (HBM2) IP. The package includes PHY, controller and verification IP and supports data rates up to 2400Mb/s, 20% faster than the JEDEC standard specification. The controller supports pseudo-channel operation in either lock step or memory interleaved mode, and the PHY offers four trained power management states and fast frequency switching. Cadence... » read more

When A Lot May Not Be Enough
By Tom De Schutter - 27 Jul, 2017 - Comments: 0

For the last couple of months my son has been trying to save for a Nintendo Switch. The emphasis here is on “trying to.” The problem is that whenever he amasses enough money to buy something else, he tends to spend the money on a cheaper toy like a new Lego Dimensions figure. I guess that delayed gratification isn’t really a strength of my son. His assumption is that the best way to colle... » read more

How Much Verification Is Necessary?
By Ann Mutschler - 27 Jul, 2017 - Comments: 0

Since the advent of IC design flows, starting with RTL descriptions in languages like Verilog or VHDL, project teams have struggled with how much verification can and should be performed by the original RTL developers. Constrained-random methods based on high-level languages such as [gettech id="31021" t_name="e"] or [gettech id="31023" comment="SystemVerilog"] further cemented the role of t... » read more

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