University of Michigan–Shanghai Jiao Tong University Joint Institute Semiconductor Engineering

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

One Chip Vs. Many Chiplets

Challenges and options vary widely depending on markets, workloads, and economics.

FOPLP Gains Traction in Advanced Semiconductor Packaging

Panel-level packaging offers scalability and cost efficiency, but meeting advanced node process targets remains a formidable challenge.

by Gregory Haley

HBM Options Increase As AI Demand Soars

But manufacturing reliable 3D DRAM stacks with good yield is complex and costly.

by Laura Peters

Asia Government Funding Surges

Taiwan, China, South Korea, and Japan continue to foster growth, while the rest of Asia competes for foreign investment and talent.

by Liz Allan

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

GDDR7 Memory Supercharges AI Inference

High bandwidth and low latency are paramount for AI-powered edge and endpoints.

by Tim Messegee

Is PPA Relevant Today?

Power, performance, and area/cost have been the three optimization targets for decades, but are they pertinent for today's complex systems?

by Brian Bailey

CXL Thriving As Memory Link

Adoption of Compute Express Link protocol spreads as way to connect memories.

by Karen Heyman

Higher Density, More Data Create New Bottlenecks In AI Chips

More options are available, but each comes with tradeoffs and adds to complexity.

by Adam Kovac

Managing The Huge Power Demands Of AI Everywhere

More efficient hardware, better planning, and better utilization of available power can help significantly.

by Ann Mutschler

Big Changes Ahead For Analog Design

In-house flows are unable to keep up with foundry PDKs and heterogeneous integration, but commercial EDA tools add their own set of challenges.

by Ed Sperling

tag: University of Michigan–Shanghai Jiao Tong University Joint Institute

Research Bits: March 22

Trending Articles

NAND Flash Targets 1,000 Layers

One Chip Vs. Many Chiplets

FOPLP Gains Traction in Advanced Semiconductor Packaging

HBM Options Increase As AI Demand Soars

Asia Government Funding Surges

Knowledge Centers
Entities, people and technologies explored

Related Articles

Shift Left Is The Tip Of The Iceberg

Memory Fundamentals For Engineers

GDDR7 Memory Supercharges AI Inference

Is PPA Relevant Today?

CXL Thriving As Memory Link

Higher Density, More Data Create New Bottlenecks In AI Chips

Managing The Huge Power Demands Of AI Everywhere

Big Changes Ahead For Analog Design

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tag: University of Michigan–Shanghai Jiao Tong University Joint Institute

Research Bits: March 22

Trending Articles

NAND Flash Targets 1,000 Layers

One Chip Vs. Many Chiplets

FOPLP Gains Traction in Advanced Semiconductor Packaging

HBM Options Increase As AI Demand Soars

Asia Government Funding Surges

Knowledge Centers Entities, people and technologies explored

Related Articles

Shift Left Is The Tip Of The Iceberg

Memory Fundamentals For Engineers

GDDR7 Memory Supercharges AI Inference

Is PPA Relevant Today?

CXL Thriving As Memory Link

Higher Density, More Data Create New Bottlenecks In AI Chips

Managing The Huge Power Demands Of AI Everywhere

Big Changes Ahead For Analog Design

Sponsors

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Recent Comments

About

Navigation

Connect With Us

Knowledge Centers
Entities, people and technologies explored