tag: Virginia Commonwealth University

Chip Industry Week In Review

By The SE Staff - 11 Jul, 2025 - Comments: 0

GlobalFoundries plans to acquire MIPS, adding RISC-V processor IP and PPA optimization software capabilities to its foundry offerings. MIPS will continue to operate as a standalone business within GF. The deal is expected to close in the second half of 2025. The EU rolled out new general-purpose AI rules this week to limit copyright infringement, protect public safety, and require transparency... » read more

Power/Performance Bits: July 3

By Jesse Allen - 03 Jul, 2018 - Comments: 0

Graphene foam devices Scientists at Rice University developed a method for building conductive, three-dimensional objects out of graphene foam, which they say could offer new possibilities for energy storage and flexible electronic sensor applications. The same lab initially created laser-induced graphene, or LIG, in 2014. The process involves heating inexpensive polyimide plastic sheets wi... » read more

Trending Articles

The Sub-2nm Paradox

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

Chip Industry Week In Review

AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; memory test facility; Taiwan investments; SiC teamup; DRAM sizing; sequentially stacking silicon; MIPI A-PHY SerDes automotive compliance.

by The SE Staff

Chip Industry Week In Review

Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon's 1.5 micron L/S litho; IC market rises; Apple's chiplet era; 4,500 chips per AI server rack; HBM price hikes; quantum IPO, chip and roadmap; SiC guidelines; MXenes; EV outlook; autonomous edge chiplets.

by The SE Staff

Toward Agentic Verification

Using AI agents for verifying designs holds huge potential, but can it deliver? And what comes next?

by Brian Bailey

Swapping Out Chiplets: I/Os Vs. Compute

Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?

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Advanced Packaging Limits Come Into Focus

Mechanical and process control limits are now shaping what can be manufactured at scale.

by Gregory Haley

Startup Funding: Q1 2026

Massive rounds for AI, EDA, and manufacturing; 80 startups raise $8.4B.

by Jesse Allen

All AI Data Center Interconnects Will Be Optical Within 5 Years

InP and SiPho join CMOS as critical technologies. Lasers, CPO and OCS will be everywhere (indium phosphide, silicon photonics, co-packaged optics, optical circuit switch).

by Geoff Tate

Making Hybrid Bonding Better

Why this technology is so essential for multi-die assemblies, and how it can be improved.

by Laura Peters

When Semiconductor Materials Misbehave

The gap between lab performance and fab reality is growing wider as packages grow more complex.

by Gregory Haley

The Sub-2nm Paradox

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

by Ed Sperling

TSMC Tech Symposium 2026, By The Numbers

Foundry rolls out aggressive new roadmap, focusing on area, power, and latency.

by Barry Pangrle

CPO Is Extending The Limits Of What’s Possible In AI Data Centers

Co-packaged optics technology will have a big impact on system power and the cost of data movement.

by Ann Mutschler

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