Technical Paper Roundup: Sept 6

Nanosheet FETs; mixed-signal DNN accelerators; manufacturing qubits; HIL simulations; GPUs & side-channel; AFM; HLS for FPGA-based accelerators; automated driving & road infrastructure challenges


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors SungKyunKwan University, Korea
Path toward manufacturable superconducting qubits with relaxation times exceeding 0.1 ms Imec and KU Leuven
Hardware-in-the-Loop Simulations: A Historical Overview of Engineering Challenges University of Maribor, Slovenia
An Algorithm-Hardware Co-design Framework to Overcome Imperfections of Mixed-signal DNN Accelerators Georgia Tech
Can one hear the shape of a neural network?: Snooping the GPU via Magnetic Side Channel Columbia University, Adobe Research and University of Toronto
High-Level Synthesis Hardware Design for FPGA-based Accelerators: Models, Methodologies, and Frameworks Università degli Studi di Trieste (Italy), Universidad Nacional de San Luis (Argentina), and the Abdus Salam International Centre for Theoretical Physics (Italy)
Road Infrastructure Challenges Faced by Automated Driving: A Review Graz University of Technology (Austria), University of Zagreb (Croatia), AKKA I&S (France)
AFM-Based Hamaker Constant Determination with Blind Tip Reconstruction ASML, RWTH Aachen University, and AMO GmbH

Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting links to papers.

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