The High Price Of Smaller Features

The semiconductor industry’s push for higher numerical apertures is driven by the relationship between NA and critical dimension. As the NA goes up, the CD goes down:

Where λ is the wavelength and k₁ is a process coefficient.

While 0.55 NA exposure systems will improve resolution, Larry Melvin, principal engineer at Synopsys, noted that smaller features always come with a process cost. Whether the area improvement is justified depends on the specific device.

Single exposure EUV has fewer process steps than self-aligned double or quadruple patterning. Indeed, the economic argument for EUV lithography rests on exactly that difference. Simplicity is not the whole story, though. The conformal spacers used in SADP and SAQP processes create a uniform grating and tend to smooth out line edge roughness. In single-exposure EUV, lithography variation transfers directly to the wafer features.

The impending transition from finFETs to stacked nanosheet designs highlights the importance of feature width control. FinFET architectures build transistors from arrays of symmetrical fins. Transistor channel width is always an integer multiple of the fin height. In nanosheet designs, on the other hand, the “fins” are parallel to the wafer surface.

Fig. 1: The etch profile of a nanosheet stack is extremely important. Tapered profiles will affect the channel width of the resulting transistors. Source: IBM Research

Channel thickness depends on nanosheet thickness and can be controlled very precisely with layer-by-layer deposition methods. Channel width, however, depends on the width of the nanosheet stack. In work presented at the most recent SPIE Advanced Lithography and Patterning conference, Eric Miller and colleagues IBM Research explained that in nanosheet transistors, variations in etch CD translate directly to the transistor dimensions.[1] Etch control is more difficult without self-aligned spacers.

Smaller CD, less depth of field
At the same time, the reduced depth of field of 0.55 NA exposure systems makes effective masking more difficult.

That is, depth of field drops more quickly than CD as numerical aperture increases.

With less depth of field, resist layers must be thinner to ensure that both the top and bottom of exposed features will be in focus. Yet, according to Arame Thiam and colleagues at imec, nearly 30% of the original resist thickness can be lost in the development step.[2] At the same time, Miller said, the features being patterned are taller and narrower. Less resist is available, but features need protection through a longer etch process. Thinner underlayers and hard mask layers may help by reducing the amount of material that the initial hard mask etch must remove.

Manufacturers are considering metal oxide resists in part to improve etch selectivity between the resist and the material being removed. Conventional plasma etching has well-known anisotropies, such as etching narrower features and wider features at different rates, or isolated features at a different rate from dense features. Those are pattern-dependent, though, not a result of true chemical selectivity. Better chemical selectivity improves the contrast between exposed and unexposed areas.

Stochastic variation affects device performance. Line-edge roughness, line-width roughness, local CD variation, and so on are due to inhomogeneities in the resist and resist process. In part, they measure the innate dimensions of the resist’s component molecules. If features shrink while molecular dimensions stay the same, Thiam said, the line-edge roughness — typically specified at 10% of CD or less — can become excessively large. Dry resists and metal oxide resists have core molecules that are smaller than the polymer chains used by chemically amplified resists, which helps. On the other hand, CAR features tend to blur due to photoacid diffusion. This blurring degrades overall resolution, but can smooth out roughness.

Though stochastic variation affects device performance, Jennifer Church and Luciana Meli of IBM Research explained that it doesn’t necessarily correlate with yield. [3] In tests at imec, Thiam’s group found that three different illumination schemes gave similar LER results, but different device yields. Process learning is slow in part because accurate yield analysis requires electrical testing for opens and short circuits.

Fig. 2: Nanosheet transistors made with single-exposure EUV lithography do not benefit from self-aligned patterning. Vertical etch profiles require careful optimization of the etch process. Source: IBM Research

Solubility defects bring circuit defects
Though smaller features are more prone to both print defects and stochastic variation, the two arise from different causes. Stochastic defects occur when an element of the intended pattern is missing, according to William Hinsberg and colleagues.[4] There might be a break in a line, or a bridge between adjacent lines. Contact holes might be missing or merged with their neighbors. These yield-limiting defects occur because the resist solubility in the defect location is different than intended by the design.

In chemically amplified resists, if the photoacid generator and quencher are in balance at a given location, the photoacid reaction deprotects the desired number of resist molecules, and then the reaction stops. If excess photoacid is present, either because of inhomogeneities in the resist or randomness in the distribution of incident photons, then more deprotection than expected occurs and the exposed resist area is larger than anticipated. (In a positive tone resist, this means that the masking layer and etched features will be smaller than intended.) With excess quencher, the opposite occurs. As the mean quantities of photons, photoacid generator, and quencher go down, the standard deviation of their distributions goes up. Defects become more likely.

While discussions of stochastic defects often focus on smaller lateral dimensions, it’s important to remember that resist layers are three-dimensional. A thinner resist contains fewer PAG and quencher molecules for a given feature size and is more vulnerable to stochastic defects.

Lots of energy, not many photons
In fact, EUV presents a dual challenge for process engineers. While Church estimated that EUV exposures deliver 14x fewer photons per unit dose, the photons that do exist have a lot of energy:

Where c is the speed of light and h is Planck’s constant.

The industry defines 13.5 nm photons as “extreme ultraviolet,” but they actually fall in the soft x-ray range, carrying more than 10 times as much energy as 193nm ArF deep ultraviolet photons. They can pass through the resist layer, exciting secondary electrons or instigating chemical reactions in the underlayer beneath. Photon-driven interactions between the underlayer and the photoresist can degrade the contrast between exposed and unexposed areas. Incomplete clearance of exposed areas leads to incomplete etching of wafer features and potential yield loss.

To minimize secondary reactions and make the most effective use of the available photons, resist designers try to increase absorption. Mohammed Alvi and colleagues at Lam Research estimated that Lam’s dry resist absorbs three to five times as many photons as chemically amplified resists.[5] But increasing absorption attenuates the exposure intensity between the top and bottom of the resist layer. The ideal resist requires just the right thickness — thick enough to protect the underlayer from EUV photons and masked areas from erosion, but thin enough to facilitate complete, uniform exposure of the entire resist layer.

Because the resist layer directly absorbs EUV photons, it is the most important piece of the pattern transfer stack. As Chris Mack put it, the areal image captured by the resist is the only indication of the designer’s intent that’s available to the process.[6] Still, Nelson Felix, director of process technology at IBM Research in Albany, N.Y., explained that it’s not enough to optimize the resist layer in isolation. The rest of the stack offers many tunable parameters, with both positive and negative consequences. Optimization of the post-exposure bake can help improve exposure latitude, by either accelerating or decelerating the deprotection reaction.

Incompatibilities between layers can lead to defects, or underlayers can help compensate for the shortcomings of the resist. Relative to spin-on resists, Alvi pointed out that Lam’s dry resist scheme facilitates very rapid process learning. Concentration of the primary photoreactive material can be adjusted at the fab, through deposition parameters. The dry develop process is similarly flexible.

As resist layers get thinner, the bulk resist properties matter less, and the interfaces between the resist — exposed or not — the developer, and the underlayer become more important. Pattern collapse, for example, depends on roughness, aspect ratio, and the surface energy of the interfaces between the resist, the developer, and the underlayer material.[7] When the capillary pressure exceeds the work of adhesion at the resist/underlayer interface, the pattern collapses. Reducing the line pitch increases capillary pressure, as does increasing the aspect ratio. Dry develop processes reduce the risk of pattern collapse as there is no capillary action.

The resist chemistry, however, is constrained by optical and etch resistance requirements. It’s difficult to optimize its surface energy as well. Instead, it falls to the underlayer to provide a uniform surface for resist adhesion and to mediate resist removal.

So many process knobs, so little time
The need to co-optimize the entire resist stack gives conventional chemically amplified resists an advantage as manufacturers try to develop high-NA EUV exposure processes. CAR resists are backed by decades of process learning and co-optimization. For now, Felix said, CAR has “achieved our goals in the current generation.” It is the incumbent technology, with a well-established ecosystem behind it. Still, high NA EUV exposure is a step change. For the next generation, metal oxide resists are at least on par, provided the rest of the process stack falls in line.

References
[1] Eric Miller, et. al., “Etch and patterning development for 2nm node nanosheet devices,” Proc. SPIE PC12056, Advanced Etch Technology and Process Integration for Nanopatterning XI, PC120560A (13 June 2022); https://doi.org/10.1117/12.2614316
[2] A. Thiam, et.al., “Towards high NA patterning readiness: materials, processes and etch transfer for P24 Line Space,” Proc. SPIE 11854, International Conference on Extreme Ultraviolet Lithography 2021, 118540A (19 October 2021); doi: 10.1117/12.2601839
[3] Jennifer Church, Luciana Meli, “Throughput vs. yield: reviewing the metrology needs for stochastics-aware process window analysis,” Proc. SPIE 12053, Metrology, Inspection, and Process Control XXXVI, 1205306 (26 May 2022); doi: 10.1117/12.2613102
[4] William D. Hinsberg, et. al., “Contribution of EUV resist counting statistics to stochastic printing failures,” J. Micro/Nanopattern. Mats. Metro. 20(1) 014603 (2 March 2021) https://doi.org/10.1117/1.JMM.20.1.014603
[5] Mohammed Alvi, et.al., “Achieving zero EUV patterning defect with dry photoresist system,” Proc. SPIE PC12055, Advances in Patterning Materials and Processes XXXIX, PC120550B (13 June 2022); https://doi.org/10.1117/12.2623499
[6] Chris A. Mack, “Reducing roughness in extreme ultraviolet lithography,” J. Micro/Nanolith. MEMS MOEMS 17(4), 041006 (2018), doi: 10.1117/1.JMM.17.4.041006.
[7] Roberto Fallica, et.al., “Adhesion and collapse of extreme ultraviolet photoresists and the role of underlayers,” J. Micro/Nanopattern. Mats. Metro. 21(3) 034601 (25 July 2022) https://doi.org/10.1117/1.JMM.21.3.034601

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