The Week In Review: Design

Multi-physics solver-as-a-service; 3nm test chip; eFPGA patent; UFS IP.

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Startup OnScale launched with advanced CAE multi-physics solvers that are seamlessly integrated with a scalable, high performance cloud computing platform built on Amazon’s AWS. The company’s model is built around a Solver-as-a-Service pay-as-you-go subscription model and targets 5G, IoT/Industrial IoT, biomedical, and autonomous car markets.

The company has $3 million in strategic seed funding led by Thornton Tomasetti, the science and engineering consulting company that spun out OnScale. Additional funding came from Michael Lehman, former CFO of Arista Networks, Palo Alto Networks, and Sun Microsystems, and CampbellKlein. The company is headed by CEO Ian Campbell, VP of Product Development Dr. Robbie Banks, and VP of Engineering Dr. Gerry Harvey. The OnScale Solver-as-a-Service will be commercially available in Q2 2018.

Imec and Cadence teamed up on the first 3nm test chip tapeout. The project utilized EUV and 193i lithography-oriented design rules and Cadence’s Innovus Implementation System and Genus Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Interconnect variation was a major challenge for the chip, according to Imec’s An Steegen.

FPGA
Efinix debuted its Trion programmable platform based on the company’s programmable technology, comprising logic, routing, embedded memory and DSP blocks. The first eight FPGAs in the Trion platform are built on SMIC’s 40nm process. The products range from 4K to 150K logic elements and support standard interfaces such as GPIO, PLLs, oscillators, MIPI, DDR, LVDS, among others.

Flex Logix was granted a patent for switch interconnects, U.S. Patent 9,906,225. Flex Logix co-founder Cheng Wang was named as the inventor. This patent builds on another interconnect patent issued to Flex Logix in late 2017, enabling the tiling of the company’s EFLX 4K eFPGA core to create more than 50 different sized eFPGA arrays from 4K to 200K.

Intel is now shipping its Stratix 10 TX FPGAs with 58G PAM4 transceiver technology. According to the company, the FPGAs provide up to 144 transceiver lanes with serial data rates of 1 to 58 Gbps. Target markets are optical transport networks, network function virtualization, enterprise networking, cloud service providers, and 5G networks applications.

Tools & IP
Synopsys launched a Universal Flash Storage (UFS) IP solution, compliant with the latest JEDEC UFS v3.0 standard. Consisting of the UFS controller v3.0, MIPI UniPro controller v1.8, silicon-proven MIPI M-PHY v4.1, verification IP, and IP Prototyping Kit, the IP doubles bandwidth to 11.6 Gbps per lane compared to UFS 2.1.

Brite Semiconductor uncorked its second generation DDR Low Power (LP) PHY IP based on SMIC 40LL process. The IP provides a 20% reduction in area, 37% in power consumption and 50% in physical implementation cycle compared to the first generation. The PHY adopts dual row IO structure and other logical and physical optimization means, which results in reducing the area of delay chains by 20%, decreasing the delay variations of DQ and DQS, and eliminating the balance of wire loadings and buffers among DQ and DQS.

Avery Design Systems announced the latest version of its SimXACT solution for analyzing X propagations in gate-level simulations. SimXACT 5.0 includes major new features for analyzing and automatically eliminating X bugs in gate-level design simulation.

Imperas released its RISC-V RV64GC Linux Extendable Platform Kit (EPK), which the company says is specifically designed to run Linux at close-to-operational performance. The platform can boot Linux in under five seconds on a regular personal computer, allowing for applications to be executed at reasonable performance levels without the need for an actual RISC-V hardware device.

Truechip shipped early adoption versions of PCIe Gen 5 and JESD204C VIP. “PCIe Gen 5 with 32 GTps will be advantageous for high end GPUs, machine learning processors and faster data transfer to Ethernet protocols being used in servers and data centers,” said Truechip CEO Nitin Kishore. “JESD204C provides for 3x faster speed compared to its predecessor JESD204B, which will allow for faster sampling at ADCs and DACs, thus improving precision by noting very quick changes.”

CEVA’s RivieraWaves Bluetooth and Wi-Fi IP platforms are now offered with an optional integrated open-source RISC-V MCU. The RISC-V implementation has a Coremark/MHz figure of 2.44 in a gate count of under 20Kgates, and the Wi-Fi RISC-V platforms scale from basic 1×1-11b-1Mbps up to 2×2-11ac/ax MU-MIMO-1201Mbps.

Deals
Chinese automotive semiconductor vendor AutoChips licensed Arteris IP’s FlexNoC interconnect IP as the on-chip communications backbone of its next-generation automotive SoC chip. AutoChips cited Arteris IP’s track record of mass production automotive chip implementations at the ISO 26262 ASIL B levels.

AccelerComm ported its polar forward error correction IP, which is utilized in the control channel of high-performance 5G systems, to Achronix’s portfolio of FPGA products. AccelerComm IP has also been integrated with ACE design tools to target Achronix Speedcore eFPGA.

Huawei inked a patent license agreement for Fraunhofer IIS’ MPEG-4 Audio patent portfolio. The license agreement addresses past and future use of Fraunhofer’s MPEG-4 Audio patent portfolio in Huawei’s products.

GEO Semiconductor selected Cadence’s Tensilica Vision P5 DSP for its new GW5400 camera video processor, which features in-camera computer vision to provide ADAS functionality.

Events
ASICs Unlock Deep Learning Innovation: Mar. 14, 3:30 p.m. – 7:30 p.m., in Mountain View, CA. This seminar will explore an implementation platform for deep learning ASICs including HBM2 and 2.5D system-in-package design and implementation. The event is hosted by Samsung Electronics, Amkor, eSilicon, and Northwest Logic with a keynote by Ty Garibay, CTO of Arteris IP.

ISQED 2018: Mar. 13-14 in Santa Clara, CA. The conference highlights design techniques and methods, design processes, and EDA design methodologies and tools to improve the quality and manufacturability of ICs. Keynote speakers will address asymmetry in electronics, opportunities in AI, and recent materials and design innovations. Tutorials focus on power-aware test, power for IoT, and cyber-physical systems.



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