Week In Review: Design, Low Power

Xilinx acquired the assets of Falcon Computing Solutions, a provider of high-level synthesis (HLS) compiler optimization technology for hardware acceleration of software applications. The acquisition will be integrated into the Xilinx Vitis Unified Software Platform to automate hardware-aware optimizations of C++ applications with minimal hardware expertise. “Our compiler provides a high degree of automation to optimize off-chip data movement, on-chip data reuse, memory partitioning, parallel and pipelined computation acceleration,” said Dr. Jason Cong, co-founder and chairman of Falcon Computing. “The single-source Open-MP like programming style is very friendly to a large base of C/C++ software developers, especially those from the high-performance computing and embedded system communities.” Based in Los Angeles, Calif., Falcon Computing was founded in 2014. Terms of the deal were not disclosed.

Imagination Technologies sold its Ensigma Wi-Fi development operations and Wi-Fi IP tech assets to Nordic Semiconductor. A number of employees will also join Nordic Semiconductor, which specializes in low-power wireless communications technology such as Bluetooth, LTE-M, and NB-IoT. “We will now be able to add Wi-Fi functionality to future generations of Nordic products,” said Nordic CTO Svein-Egil Nielsen. “We feel extremely fortunate to have found the perfect Wi-Fi team with decades of state-of-the-art design experience and expertise. We believe in owning every link in our product chain, and with the Imagination Wi-Fi team on-board we will now be able to deliver to our customers Wi-Fi hardware and software that Nordic has developed from the ground up, as we do with all our other wireless product ranges.” Terms of the deal were not disclosed.

Arteris IP completed its acquisition of Magillem Design Services assets. Magillem is now the IP Deployment Division within Arteris IP, with IP deployment technologies available as standalone products for current and future Magillem customers. They will also be integrated with Arteris IP NoC interconnect IP. Arteris said it hired “substantially all” Magillem employees into its French subsidiary. Based in Paris, France, Magillem was founded in 2006.

Tools & IP
Codasip unveiled three new 64-bit RISC-V application processor cores. The A70XP includes a SIMD unit which executes RISC-V P extension instructions with single-cycle latency. Multi-cycle instructions are pipelined to allow one to be executed every clock cycle. Applications include audio encoding/decoding, sensor fusion, computer vision, and edge AI/ML applications. The A70X-MP and A70XP-MP cores add multi-core features, supporting clusters of up to four cores in a symmetric multi-processor (SMP) configuration. Codasip provides configurable L1 and L2 caches with a scalable microarchitecture. All use an AXI external interface and support Linux, are 64-bit, and feature a Floating Point Unit and Atomic instructions.

Mobiveil debuted Compute Express Link (CXL) 2.0 Design IP and announced successful completion of CXL 1.1 validation with Intel’s CXL host platform. The COMPEX IP is a highly configurable, low-latency CXL controller that supports up to 16 lanes on a flex bus interface and is compliant with the PIPE 5.2 specification. It provides a simple packet-based interface-to-user logic that supports 128-bit, 256-bit and 512-bit data path widths.

Andes Technology added to its lineup with high performance superscalar A45MP and AX45MP multicore processors, as well as A27L2 and AX27L2 processors with Level-2 cache controller. The AndesCore 45-series IPs are in-order 8-stage dual-issue RISC-V processors equipped with optional DSP (RISC-V P-extension) unit, single or double precision Floating Point Unit and Memory Management Unit that also supports Linux-based applications. The 27-series inherit the MemBoost feature, where multiple outstanding data accesses and I/D cache prefetch boost the memory subsystem performance.

T2M-IP uncorked a PCIe Gen5 PHY IP Core and PCIe Gen4 PHY IP Core on TSMC 12FFC 12nm FinFET process with matching digital Controller IP Cores. The cores exceed PCI-SIG’s compliance spec in jitter tolerance and insertion loss and use additional PLL control, reference clock control, and embedded power gating control for lower power consumption.

IAR Systems expanded its IAR Embedded Workbench for RISC-V with additional trace functionality and new compiler optimizations. It adds support for Nuclei System Technology devices, as well as enhanced implementation of the draft P extension and intrinsics with support for the vectorized versions.

Deals
Samsung Foundry qualified Synopsys’ full flow for 5nm to 3nm designs targeting 5G, AI, and HPC SoCs. The signoff flow covers multiple domains including full-chip signoff, static timing analysis, design closure, power analysis, extraction, and library characterization.

Rockley Photonics utilized Cadence system analysis and custom tools to design a state-of-the-art, high-performance System-in-Package (SiP) for hyperscale data centers with first-pass success. The SiP is comprised of discrete chiplets connected through a high-speed 112G PAM4 serial interface.

Andes Technology and Imperas Software teamed up to make fast simulators and virtual platforms available for the Andes Custom Extension framework. The ACE framework for Andes RISC-V processor cores allows designers to define custom instructions and have all the required components generated automatically in no time on their desktops by the COPILOT tool. They include extended components for the processor RTL, the compilation tools, the debugger, the cycle-accurate simulator as well as the Imperas fast functional simulators.

5G
Wireless carriers in the U.K. will be blocked from installing Huawei equipment in 5G networks starting in September 2021, reported CNBC. Telecom operators will no longer be able to buy Huawei 5G equipment by the end of the year, and any currently installed will have to be removed by 2027. The U.K. is also putting money into diversifying the 5G supply chain and will create a National Telecoms Lab research facility alongside funding a trial with Japan’s NEC to develop open radio technology for 5G.

Ericsson expects there to be 220 million 5G mobile subscriptions by the end of the year, 30 million more than it previously predicted, according to Reuters. Faster than anticipated adoption in China is driving the increase, with the county expected to make up 80% of the new total.

Numbers & People
Synopsys reported fourth quarter 2020 financial results with revenue of $1.025 billion, up 20.4% from the fourth quarter of last year. On a GAAP basis, earnings per share for Q4 2020 were $1.26, up 21.2% from $1.04 in Q4 2019; non-GAAP earnings were $1.58 per share, up 37.4% from $1.15 per share in the same quarter last year.

For the full fiscal year, the company had revenue of $3.685 billion, up 9.6% compared to FY2019. On a GAAP basis, FY2020 had earnings per share of $4.27, up 23.8% from $3.45 last year. Non-GAAP earnings for the year were $5.55 per share, up 21.7% from $4.56 last year. Chairman and co-CEO Aart de Geus said, “In fiscal 2021, we aim to surpass $4 billion in revenue, with continued non-GAAP operating margin expansion, low-to-mid teens non-GAAP earnings per share growth, and more than $1 billion in operating cash flow.”

DRAM is set to be the IC category with the largest revenue in 2020 with sales of $65.2 billion, according to market research firm IC Insights. NAND flash follows with $55.2 billion in sales, also giving it the largest increase, 25%, compared to last year’s sales. Just behind NAND for increase in sales is cellphone processors, which increased 24% to $26.6 billion in 2020, making it the fifth largest segment by revenue.

Silicon Integration Initiative selected Dr. Leigh Anne Clevenger as director of OpenStandards, effective January 1, 2021. She will replace Jerry Frenkil, who served in this role since 2015. Since joining Si2 in 2018, Clevenger has been the lead developer of the Si2 prototype power calculator, demonstrating the UPM/IEEE-2416 standard. She will continue to drive the UPM working group toward its goals of developing and adopting the standard.

Events
Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

The RISC-V Summit 2020 will take place Dec. 8-10. The Asia and South Pacific Design Automation Conference 2021 will happen Jan. 18-21.