SRC/NIST packaging roadmap; CHIPS Act caveats; “Fab 4” alliance for resilient supply chains, eBeam Initiative adds IBM, EUV Tech; chip revenues fall.
Semiconductor Research Corporation (SRC) released an interim roadmap for Microelectronic and Advanced Packaging Technologies (MPAT) that targets 10- to 15-year goals for 3D integration and multi-chiplet packaging. The roadmap is open for comments. Participants in the MPAT include AMD, IBM, Intel, Texas Instruments, Purdue University, SUNY Binghamton and the Georgia Institute of Technology. It is funded by a grant from the National Institute of Standards and Technology (NIST).
Imec uncorked a virtual fab modeling platform at this week’s SPIE Advanced Lithography + Patterning Conference, which quantifies the environmental impact of fabs. “We demonstrated that lithography and etch together are responsible for 45% of the Scope 1 and Scope 2 emissions (i.e., emissions from owned/operated assets, and from purchased energy, respectively) associated with fabricating 3nm logic wafers,” said Emily Gallagher, principal member of the technical staff at imec. “Together with physical fab results, the tool can highlight high impact areas such as reducing fluorinated etch gases and water use or maximizing EUV scanner throughput.
Also at the conference, the eBeam Initiative announced two new members, IBM and EUV Tech. EUV Tech, meanwhile, said it received Series A funding led by Intel Capital. The startup manufactures an actinic EUV mask imaging and defect review system, pellicle mapping, and phase measurement systems.
The White House and the U.S. Chamber of Commerce opened funding applications and stipulated conditions for CHIPS Act applicants. Among other requirements, companies must not engage in significant expansions of chipmaking capacity for 10 years in countries of concern. Companies receiving awards also must commit to a diversified workforce, provide access to affordable childcare, and share excess profits.
In support of the CHIPS Act goals, MITRE Engenuity and its alliance released a position paper on the planned National Semiconductor Technology Center (NSTC) that identifies the key factors to achieving a more resilient semiconductor manufacturing ecosystem in the United States.
Meanwhile, Reuters reported the first video meeting was held by the U.S.-led “Fab 4” semiconductor alliance, which includes Taiwan, Japan, and South Korea. The meeting focused on improving global supply chain resilience following the Covid 19 disruptions and the impact of U.S.-China trade restrictions.
Recent analyses confirm reductions in global semiconductor revenues and shipments, led by DRAM. Trendforce reports global DRAM revenue fell by more than 30% in 2022, while global data center CPU revenue declined 4.4%, according to Counterpoint Research. The top 10 OEMs decreased overall chip spending by 7.6% in 2022, according to Gartner.
Infineon Technologies will acquire GaN Systems in a $830 million deal. “Combining GaN Systems’ foundry corridors with Infineon’s in-house manufacturing capacity enables maximum growth capability to serve the accelerating adoption of GaN in a wide range of our target markets,” said Jochen Hanebeck, CEO of Infineon.
Swedish wafer manufacturer, SweGaN, announced the construction of a new high-capacity epiwafer production facility in Linköping.
Bruker introduced the new SKYSCAN 2214 CMOS Edition, a 3D X-ray inspection system based on nano-CT (computed tomography) that can detect defects as small as 500nm using up to four detectors.
JCET provided multiple customers with two advanced packaging HVM solutions for 4D mmWave radar optimized for assisted and autonomous driving applications. JCET’s proprietary fan-out eWLB solution offers lower parasitic resistance in a thinner package for mmWave radar transceiver chips. SOCs with integrated antenna are best suited for its flip-chip chip scale package (FCCSP) approach.
UMC unveiled a new 28eHV+ platform, the newest enhancement to its industry-leading 28nm embedded high voltage (eHV) technology, a display-driver solution to power next-generation displays used in smartphones, virtual and augmented reality devices, and IoT. The device offers a smaller SRAM bit cell, leading to smaller overall chip size.
Applied Materials introduced the VeritySEM 10 system, which offers lower landing energy than traditional systems to minimize adverse effects on thin EUV photoresists.
JEDEC published three new guidelines for reliability and testing of silicon carbide MOSFETs. JEP194 establishes procedures for evaluating of reliability of gate oxide, including time-dependent dielectric breakdown (TDDB) testing and interpretation. JEP195 addresses the SiC MOSFET-specific phenomenon called gate switching instability and includes test and measurement routines to evaluate parametric drift and its effect on device performance. JEP192 describes the test method for gate charge of SiC MOSFETs that takes into account unique performance attributes of SiC MOSFETs.
An international team of researchers demonstrated a switch made from a single molecule of fullerene that is 3X to 6X faster than current microchip switches.
A new type of optical nanoscopy that can measure electron dynamics in semiconductors has been developed by researchers at UC Berkeley.
Check out our February Manufacturing, Packaging and Materials newsletter, including these top stories:
Read our February Test, Measurement & Analytics newsletter for these highlights and more:
Upcoming events in the chip industry:
Upcoming webinars:
The Data Revolution Of Semiconductor Production – How Advancements in Technology Unlock New Insights: Mar. 7
Accelerating Front-End Semiconductor Process Control with Accurate Metrology and Characterization: Mar. 15
 |
 |
 |
 |
 |
 |
 |  |
Leave a Reply