What Exactly Are Chiplets And Heterogeneous Integration?

The terms “chiplet” and “heterogeneous integration” fill news pages, conference papers, and marketing presentations, and for the most part engineers understand what they’re reading. But speakers sometimes stumble during a presentation trying to figure out whether a particular die qualifies as a chiplet, and heterogeneous integration comes in different guises for different people. Both terms lack well-accepted definitions that can help navigate the nuances that now bedevil the terms.

For some industry experts, the presence of a die-to-die interface qualifies a piece of silicon as a chiplet. There is much more disagreement when it comes to heterogeneous integration, and when pushing and pulling on different criteria during a discussion, one person’s definition may shift. Today, this discussion could feel pedantic, but in the long term, clear and consistent definitions could spur growth in this nascent architecture.

What’s a chiplet?
Chiplets are a popular topic today, thanks to the evolution of heterogeneous integration (more on this later). The disaggregation of an SoC into discrete components is significant on one level. But integrating multiple dies into a single package is far from new. Multi-chip modules (MCMs) have done this for years, mostly for non-mainstream applications that receive little attention.

In an MCM, the constituent components are typically chips that would otherwise be sold separately in packaged form. Absent a custom implementation, nothing new was required of the components within the MCM package.

So are chiplets merely a new name for what we’ve been doing for years? Despite some disagreements on defining details, no one views chiplets as simply a new name for an old thing. The key feature identifying chiplets for most (but not all) is a dedicated way to connect one die directly to another. “It would need some level of die-to-die interface within it,” said Michael Posner, vice president of product management for high-performance computing IP solutions at Synopsys.

Some suggest that only silicon with a standardized die-to-die interface should qualify. “For us, the only point to say a chiplet is a chiplet is if we have a standardized interface between the chips,” said Andy Heinig, group leader, advanced system integration, department head of efficient electronics at Fraunhofer IIS EAS. Otherwise, the assembly is just an MCM.

Although a new interface isn’t strictly necessary, as existing MCMs prove, chiplet integration can improve performance and efficiency in ways that a chip in an MCM cannot. “A traditional chip is designed to be put in a package on its own, and then has to be able to drive a printed circuit board (PCB) line on its own,” said Marc Swinnen, director of product marketing at Ansys. “So it has big drivers on the I/Os to drive these outside lines. A chiplet, on the other hand, is intended for use in conjunction with other chiplets on an interposer. Hence, its interface is going to be much higher speed and lower power, and it can drive only a few millimeters of wire. That chiplet can never be put in a regular package because it doesn’t have the drive strength to drive a normal wire.”

The whole chiplet idea originates from economic concerns about the cost of advanced nodes, as well as the inability to produce die larger than reticle size. “Chiplets result in improved overall yield and costs since they are assembled using smaller, individual known-good die and a fabrication technology suitable for each die — as opposed to integrating all functionality at a large die level with the most technologically advanced fabrication node necessary to achieve the most demanding function within the device,” said Dave Fromm, COO of Promex.

Many companies today employ proprietary schemes to move data more efficiently from die to die. That qualifies such dies as chiplets for many people. For those that want standardization, UCIe and Bunch of Wires (BoW) add that imprimatur, and uptake has begun.

The issue of standards is important mostly for the broad notion of chiplets being available in an open market in the way IP is today. Interoperability becomes critical to ensure that any chiplets purchased from different sources will play well together. And for some, this is really what a chiplet is about, and it’s why they feel a standardized interface is necessary to qualify as a chiplet.

Variations on the theme
A slight relaxation of this approach comes from Arm, which focuses more on disaggregation than the interface. “A chiplet is an unpackaged silicon die designed to be combined and packaged with other chiplets and operate as part of a system on chip (SoC),” said Mark Knight, director of architecture product management at Arm. “Chiplets create larger, more complex systems that can be packaged and sold as a single component, with each chiplet being optimized for a specific function or task. This eliminates the need to build one large monolithic die, which can present cost-efficiency challenges and cause yield-related economic issues.”

The chiplet-market notion complicates things, and Synopsys makes a distinction based on that. “Because ‘chiplet’ was also used to describe this open chiplet marketplace, we started using the term ‘multi-die’ because it goes across all the markets and use cases,” said Posner. Given this definition, only a die designed for that open market would be a chiplet. But he still sees having a die-to-die interface as necessary.

Another view focuses on the role the die plays in the package rather than the interfaces. If it’s independent, then it’s not a chiplet. “Chiplets are modular,” said Pratyush Kamal, director, central engineering solutions at Siemens EDA. “Different chiplets designed to perform specific functions are combined together on an interposer within a single package.”

But specific functions are not necessarily standalone functions. “It requires the die to be packaged with other functions,” said Synopsys’ Posner. “It doesn’t necessarily mean it’s small. We are seeing reticle-size dies being packaged together.”

By this definition, a set of chiplets must be regarded together and cannot be considered individually to be complete functions. “When you look at boot, debug, test, the clock, or power management, you have to look at the multiple entities together,” said Kamal. “You can’t look at them in isolation.”

And internal latency must be nominal. “Die-to-die latency has to be a small portion of your total latency,” he said. “Only then you could say that it’s tightly coupled with another entity.”

Although packaging would seem to be an important part of the chiplet notion, even that isn’t viewed as being universally required. “The industry is leaning toward putting the essential constraint that a chiplet has to be co-packaged,” said Kamal. “I don’t necessarily agree with that, because you could have a system where it may be economical to have the two chiplets directly mounted on the board.”

What’s a chip?
Related to this discussion is what we should call that little piece of silicon. Is it a die or a chip? With one die per package, that was never a question. Now multiple components are being packaged together, is the “chip” the die or the packaged unit? Many people are assigning “die” to the single piece of silicon, while “chip” is a packaged unit, regardless of the contents.

“Normally, a chip is something tested and packaged, ready to be shipped and assembled into devices,” said Pax Wang, director for advanced packages at UMC. “However, a chiplet refers to different functional chips (or dies) tested and packaged into the same chip.”

Fig. 1: Chip vs. chiplet. The left illustrates a device where ‘chip’ is defined by some as a packaged product ready to solder to a PCB. The right shows a collection of components, some of which are chiplets, being integrated into the same package. Source: UMC

That distinction isn’t driven by technical considerations, but by convenience — we need terms for these things. The challenge is when not everyone gets the memo on the names. It also conflicts with the older multi-chip module terminology, where “chip” refers to a die, so even here clarity is tough to achieve.

n this basis, some people prefer the term “dielet” to “chiplet,” because what we call chiplets don’t look like smaller versions of a packaged circuit. “When developing wafer stacking services for customers, I believe ‘dielet’ could be better than ‘chiplet’ in some circumstances,” said Wang. But “chiplet” sounds better than “dielet,” so for the time being, any of us who aren’t fans of “chiplet” are stuck with it.

Analog and optical complicate things
Things get more complicated when an analog die is included in the package. The standardized interfaces are digital and apply to any control signals or digital data being converted to or from analog. Analog signals obviously would not make use of any such interfaces. If the analog signals drive or are driven solely by external signals, then it has no need for any special internal interface. If analog is driving another chiplet, however, that connection would need to be custom-designed and custom-verified.

So if the litmus test for a chiplet is the existence of the standardized interface, then an analog die would qualify as a chiplet only if it had those digital signals. If those signals provide control rather than data, it’s unlikely it would require the bandwidth of a standardized interface. Whether it still made sense to employ that interface or something simpler would be a decision for the architects.

But this is where things get a little funky. If one accepts the standardized interface as sacrosanct, then some analog chips may not qualify as chiplets. If any die-to-die interface qualifies without requiring a standard, then more analog chips would qualify.

Photonic chips have the same potential issue, although it’s probably too early to worry about it. A purely photonic chip will have no electrical interfaces. So can it still be considered a photonic chiplet?

This is where these definitions run into a general test. If some criterion — such as a standardized interface — must be satisfied to qualify as a chiplet, with some dies having it and some not, does it make a difference? If some hypothetical analog chip had no digital signals and therefore didn’t qualify as a chiplet, does that mean it can’t be integrated into a package? Of course not. So that’s where debating these definitions can help communication, but living rigorously by them may not be as important.

Fig. 2: Summary of chiplet definitions from our interviews. The most common one requires a die-to-die interface. Other definitions are more scattered. Source: Semiconductor Engineering

Heterogeneous integration is messier
Heterogeneous integration is also a new concept. “For 30 or 40, years, we’ve gone toward monolithic design, and there were huge advantages,” said Swinnen. “If you have multiple cores and put them all on one SoC, they would be faster, smaller, and cheaper, and they would have lower power. That still exists. The only reason you might not be able to do that is that the chip gets too big.”

Another factor is simply the cost of advanced nodes and the desire to avoid that cost if it doesn’t add value. “Certain chips (e.g. memory, CPUs, GPUs) aren’t valued if they don’t ‘keep up,’ and those are the ones that migrate to the leading edge,” said David Park, vice president of marketing at Tignis. “But other chips don’t need to migrate to a smaller process node.”

Verification and processing considerations also play a role. 2.5D integration gets much of the attention these days, but 3D can compound integration issues. “Integration challenges emerge when you try to connect different 3D components,” noted Benjamin Vincent, worldwide senior manager of semiconductor process and integration at Lam Research, in a blog post. Those challenges can motivate the “heterogeneous” distinction.

Whereas varying definitions of “chiplet” are close, there’s more diversity in how engineers view heterogeneous integration. They all account for multiple things in a package, but there are different “lines” for defining it as heterogeneous. “I don’t see there’s a very clear definition for this,” noted Wang. Those lines escalate as follows:

• Having multiple items in the package is enough. It can simply be two of the same die. “Heterogeneous integration is typically dies with different functions being packaged together,” said Posner. “But part of that could also be compute scaling. [Having four of the same die] would still be heterogeneous integration.”
• Multiple dies must be different. “It can be easier to define the opposite of heterogeneous integration first,” said Knight. “A system composed of several identical CPU chiplets is not heterogeneous. A system composed of different chiplet types is a heterogeneous system.” Promex hews to a similar definition: “We define heterogeneous integration as a methodology for assembling diverse components — electronic and non-electronic — into a single compact device,” said Fromm.
• Different dies must be independently designed, as opposed to one coordinated project. Those dies may or may not come from the same company.
• Packages must contain a mix of process nodes. “My personal definition is, if two chiplets come from the same node, that’s homogeneous integration,” said Wang. “If we connect DRAM to logic, it definitely leads to wafers that come from different nodes, so this is heterogeneous integration.”
• Packages must contain a mix of advanced and mature nodes. “We can integrate an old technology node for high voltage for actuators or sensors together with 5nm processing elements,” said Heinig. “This is what we understand as heterogeneous integration in Europe. If Intel or AMD is combining 7nm with 12nm, it’s not heterogeneous for us because they don’t face all the same problems.”
• Packages must integrate different materials. “DARPA focuses on the material,” said Kamal. “Even something as fundamental as a silicon interposer with a plastic substrate is heterogeneous integration.”
• Either mixed nodes or mixed materials will qualify. “Early on, many participants thought of heterogeneous integration as different silicon nodes used in a multi-chip or chiplet solution,” said Melissa Grupen-Shemansky, CTO and vice president of technology communities at SEMI. “Some technical professionals still see it as the integration of chips from different nodes. But it can also include chips of different materials, like silicon and germanium, and compound semiconductors like GaN and InP.”

Some of those considerations are relatively brittle. For instance, given the requirement for different nodes, then if a package contains a 22nm die and a 12nm die, it’s heterogeneous. If at some point in the future the 22nm die is upgraded to 12nm, now it’s no longer heterogeneous by that definition.

How does the definition help?
So what is the “heterogeneous” distinction supposed to convey? In this example, nothing really changes in the assembly process. It’s just that one die was updated. It’s not clear that changing from heterogeneous to homogeneous provides any substantive clarity.

“Even if they share the same node, if they have totally different functions, totally different design concepts, and totally separate roadmaps, I would call it heterogeneous integration,” Wang said.

Here again, analog complicates things. “Analog doesn’t use advanced nodes,” Swinnen said. “There are so many parasitic effects that come out of the woodwork at 5nm that it becomes difficult to meet spec.”

One view of the heterogeneous distinction is the understanding that the whole package must be simulated together to ensure a product that will perform and yield as desired.

“If you have 100 V on one chiplet, you have to make sure it doesn’t couple into your 5nm subsystem,” said Heinig. “That’s a multi-physical problem. A second problem that we see is that, if you look at BoW and UCIe, the interface voltage is around 0.7 or 0.8 V. This works very well for 7nm, 10nm, or 22nm, but if you go to 65 or 90nm, your supply voltage is 3 V or 5 V. Then, the 0.8 V on the interface doesn’t work because you are not reaching the threshold voltage of the mature technology.”

The necessary simulation grows with additional materials, because multi-physics simulation will confirm thermal performance, reliability, noise, signal quality, and any other considerations for a robust product. “You could have a subsystem spanning multiple technologies,” said Kamal. “You need to extract and simulate that as a whole, and that’s why we need this emphasis on heterogeneity.”

Rounding out the discussion, IEEE publishes a heterogeneous integration roadmap, and it aligns with the most lenient definition: “Heterogeneous integration refers to the integration of separately manufactured components into a higher-level assembly that, in the aggregate, provides enhanced functionality and improved operating characteristics.”

Fig. 3: Summary of heterogeneous-integration definitions from SE interviews. Responses are widely spread among the criteria. Source: Semiconductor Engineering

So who cares?
One can argue subtleties of definitions, but will that effort have a payoff? Generally, a definition is useful if it yields information that helps decision-making. For chiplets, the value of the definition depends on the context. A company doing its own SoC disintegration can use its own nomenclature.

But if a chiplet market emerges, interoperability hinges on a purchased product qualifying as a chiplet. Of course, if someone sells a “chiplet” on the open market — one that doesn’t have a die-to-die interface but otherwise works — is that really a problem? As long as the die is well documented, probably not.

Heterogeneous integration may be another matter. Today, everyone is developing their own flow for advanced packaging, and those flows differ from each other specifically because these companies are trying to differentiate their processes. Moreover, many projects proceed individually rather than benefiting from a recipe.

But if those recipes start to separate into two distinct tiers — one for homogeneous and one for heterogeneous — then the designation will determine the recipe. Ideally, all companies engaged in packaging would agree on the same definition so that planners shopping around can make apples-to-apples comparisons rather than having to wade through varying definitions.

Clearly the chip industry is not there yet, so for now the discussion has most value as an opportunity to think about what the most appropriate definitions are. With luck, such cogitations will start to align as practical implications become more evident.

Related Reading
Navigating Increased Complexity In Advanced Packaging
Variability is a growing challenge; achieving higher yields requires even tighter control and precision.
Signal Integrity Plays Increasingly Critical Role In Chiplet Design
Chiplet design engineers have complex new considerations compared to PCB concepts.
What Exactly Is Multi-Physics?
The chip industry’s new buzzword comes with lots of implications and some vague definitions.