Updated. Applied Materials and Lam Research have rolled out ALD and etch tools to deal with processes at the atomic level.
Chipmakers are ramping up a new range of device architectures, such as 3D NAND and finFETs. But to enable current and future devices, IC vendors will require new breakthroughs, including tools that can process tiny structures and films, even at the atomic level.
The problem? There are gaps in terms of techniques that can process chips at the atomic level.
Looking to help fill part of the gap, Applied Materials has rolled out a next-generation atomic layer deposition (ALD) tool and a new etch system. And at this week’s Semicon West trade show in San Francisco, Lam Research and others are bringing out tools in the arena.
There is a pressing need for such tools. “If you look at the roadmaps, there are so many small and big innovations that are needed,” said An Steegen, senior vice president of process technology at Imec, in a recent interview. “You cannot pin it to one. The fact that EUV is needed is clear. We also need the right ALD materials. The dimensions are so small. So how you basically build the stacks on top of each other is critical.”
Current and future devices will require structures with thin, precise and conformal films. And chipmakers will continue to deal with chips equipped with a finite number of atoms. For example, Intel’s first-generation finFETs, which are based on a 22nm process, have only 19 atoms across the critical part of the fin structure. “The (etch) control has to be a lot less than that. Typically, it’s 10%. So you are down to a two atom control,” said Uday Mitra, vice president and chief technology officer for the Etch Business Unit at Applied Materials.
Just to measure the lateral portions of these structures with today’s metrology tools is also a feat. “Semiconductor manufacturers require under 0.5 angstroms,” said Keibock Lee, president of Park Systems, a supplier of atomic force microscopy (AFM) tools. If an angstrom is 0.1nm, then 0.5 angstroms is 0.05nm.
Down to the atomic level
To process chips at the atomic level, there are various solutions in the market today. For years, ALD has been used to scale the capacitor in DRAMs as well as to develop the high-k/metal-gate stack for logic devices. More recently, ALD is also being used to deposit films for the spacers in multiple patterning applications.
In total, the ALD business is expected to reach $920 million to $925 million in 2015, up from $830 million in 2014, according to Applied Materials. Applied Materials, ASMI, Lam, TEL and others compete in the ALD tool market.
ALD is a deposition technique that deposits materials one layer at a time. “ALD is the alternation of two different chemistries being introduced in a sequential manner,” said David Chu, strategic marketing director at Applied Materials. “Because the chemistries are being broken up, it’s self-limiting. That’s why it allows the technology to be conformal.”
But it’s also no secret that ALD is a slow process. “You are getting to the point where conventional ALD is just simply running out of steam,” Chu said. “We have things like patterning, capacitor dielectrics or future 3D NAND. Those things are still on the order of about 100 angstroms or 200 angstroms. Using conventional ALD to grow 200 angstrom films ends up being a challenge.”
In response, Applied has rolled out a new ALD tool, dubbed Olympia. The product is a new platform designed for 10nm and beyond. It is geared for various applications, such as low-temperature films, patterning, selective deposition, high-k and low-k.
In traditional ALD tools, the wafers are stationary. The chemistries enter the chamber and they process the wafers. Then, the chemistries are purged, which is a slow process.
In contrast, Olympia is a modular architecture. Basically, wafers can be placed in the system. The wafers travel continuously to various zones. Each zone has a different type of chemistry. The zone isolates the individual chemistry.
The Olympia system’s modular architecture enables a flexible and rapid process sequence vital for controlling the more complex chemistries needed to develop the next generation of ALD films. All told, the tool boosts ALD productivity by fourfold. It eliminates the purging process, thereby speeding up ALD.
In addition, chipmakers can configure the system to support a number of zones and chemistries. “The permutations are endless,” Chu said. “For example, I can put a treatment between (chemistry) A and B. In addition, I can do three chemistries. I may even able to do three chemistries and a treatment.”
Meanwhile, Lam Research has released its Vector ALD Oxide system on the Extreme platform. The new product from Lam uses ALD to create conformal dielectric films, especially for spacer-based multiple patterning.
To enable scaling for 14nm and below, chipmakers are adopting self-aligned schemes, including self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). These deposition processes are challenging since they must form conformal and uniform films. For example, a 200-to-300 angstrom-thick film can have only a few angstroms thickness variation across the wafer.
For 10nm processes, the manufacturing complexity will continue to increase as additional multi-patterning process steps are added with each step contributing to overall CD variability. The Vector ALD Oxide system, according to Lam, supports the uniformity required for CD control for SADP and SAQP schemes. The quad-station modules process four wafers simultaneously. The system delivers as much as 20% higher footprint productivity compared with other solutions, according to Lam.
The tools from Applied and Lam bring the industry closer to a technology called selective deposition, which selectively deposits materials in exact places at the nano-scale. One form of selective deposition, dubbed ALD-enabled nano-patterning, is still in the R&D labs. In addition, a related technology is called selective removal or atomic layer etch (ALE), which is a next-generation etch technology that is also in R&D.
ALE won’t replace today’s plasma etchers. In fact, reactive ion etch (RIE) continues to extend and is even becoming more critical in the fab flow, especially in multi-patterning, high-aspect ratio etch and others.
“The big challenge for scaling, at least for etch, is getting the uniformity right,” said Amulya Athayde, senior director of global product management at Applied Materials. “In the case of NAND, you have this huge inflection because of 3D NAND, where the aspect ratios are going through the roof.”
Etch control is also challenging. “Variation control is really dropping down to the atomic scale,” Athayde said. “Gate CDU uniformity requirements are in angstroms not nanometers.”
In response, Applied Materials also rolled out the Centris Sym3 Etch system. The system features a new etch chamber built from the ground up. “If you look at the 300mm etch products in the market today, most of them were developed about 15 years ago at the initial introduction of 300mm,” he said. “We felt it was time to develop a new chamber from the ground up.”
The Centris Sym3 platform’s six etch and two plasma clean process chambers feature system intelligence software to ensure that every process in every chamber matches, enabling repeatability and high productivity. “The tool is for 10nm and beyond,” Applied’s Mitra said. “The main difference is basically the chamber architecture. It’s fully symmetric. Because of the high conductance, it can take care of etch byproducts.”
It employs so-called True Symmetry technology with multiple tuning controls. This, in turn, enables process uniformity on the structure. “It’s a methodology that allows us to get to less than half-nanometer CDU uniformity across the wafer,” Athayde said.
“It also allows us to run higher flows. Higher flows might sound like a trivial thing. But the flow is limited by the chamber design. Just sticking a larger pump on a small chamber is not going to give a benefit,” Athayde said. “With the Sym3, we are able to tune this energy and angle of distribution. We have a much wider distribution of ion energies.”
Key to the design is a focus on controlling and removing etch byproducts, which are hampering within-chip patterning uniformity. The system mitigates byproduct re-deposition to overcome the challenges of line edge roughness, pattern loading and defects. Combined with an advanced RF technology that controls ion energy and angular distributions, the Sym3 system delivers vertical profiles for high-aspect ratio 3D structures.
And not to be outdone, Lam Research has introduced the Flex G Series for high-aspect-ratio (HAR) dielectric etch. The tool enables the continued scaling of DRAM and 3D NAND devices.
The HAR capacitor cells and vertical transistor channels within these devices require the formation of distortion-free vertical profiles from the top to the bottom of these tall, narrow features. Built upon Lam’s Flex product family, the new system meets these challenges by combining high ion energy, advanced process uniformity tuning, and proprietary RF pulsing, according to the company.
“Advanced memory device designs involve increasingly high-aspect-ratio dielectric etch applications,” said Vahid Vahedi, group vice president of Lam’s Etch Product Group. “These require etching through very deep structures with process control. Using technology that enables tuning critical process parameters like etch profile and mask selectivity, our new Flex G Series is designed to help our customers address their most difficult challenges.”