The next phase of development will require a bunch of technologies, and a new way of thinking about how to use them.
For all the chatter and occasional tirades about EUV missing its market window—it’s true, EUV will have missed five market windows by 10nm—it still matters. And the sooner EUV hits the market with a viable power source, the better off the entire semiconductor manufacturing industry will be.
But even EUV is a sideshow to some important shifts underway in technology. While technologically it’s entirely possible to hit 1.5nm (and well into the Angstrom world after that), those kinds of measurements will become increasingly irrelevant. After 3nm, and maybe even as early as 7nm, it’s likely that lithography will include a combination of technologies ranging from directed self-assembly to carbon nanotube FETs. Some metal layers still will require old-fashioned lithography, and EUV will be one of the choices, maybe even in conjunction with multi-beam e-beam and direct write and nanoimprint.
But the new reality is that as chips become a complex array of platforms, lithography will follow the chip architecture rather than dictating it. EUV is great for some applications, and directed self-assembly is better for others. And then there are openings for additional lithography approaches such as multi-beam e-beam and direct write as those begin to demonstrate their capabilities.
While some industry insiders continue to rail about EUV’s delays and the havoc it has caused, it’s not that simple. Multi-patterning is more expensive and time consuming, but no one really knows what EUV will cost. It could turn out that, after billions of dollars of investments, EUV might be more expensive even if it is faster—so far, no one knows. And no matter what happens, at 7nm even EUV will require a double exposure. At 5nm, there may be so many exposures that pre-built platforms connected with through-silicon vias or interposers or something in between are the only way to hit market windows at a reasonable cost.
The semiconductor industry has been on a trajectory to put more and more functionality and components on a single die in an effort to trim costs and improve performance. As features continue to shrink, though, the next big turn of the crank on performance, cost and power will be less about cramming stuff on a single piece of silicon and more about shortening and widening the pathways. EUV will still play a role here, but so will a lot of things.
This is good news for the entire semiconductor industry. It opens the doors to creativity and new ways of doing things once again, rather than racing to the beat of Moore’s Law. It’s not that Moore’s Law won’t continue in some areas. Intel, for one, is committed to hitting the next few nodes using the same road map it has been following since the mid-1960s. But even Intel is now offering 2.5D configurations in its foundry with off-die memory. And that’s just the beginning.
Lithography has provided a means for the semiconductor industry to lower cost while improving performance at a rate that even Henry Ford would appreciate. But it’s easy to lose track of the focus on lower cost and improved performance, not to mention the new wrinkle of lower power. These were always the real goals, and the way to achieve them has shifted—mostly due to the laws of physics. Lithography is only one piece of the puzzle, and progress from this point onward will require multiple technologies and approaches, new alliances, and a fundamental restructuring of the supply chain. But most of all, it will require a mindset that is open to change and a sizeable dose of hubris to make it happen.