Getting Over Overlay

Solutions are being developed, but there are questions about how effective and efficient they will be.


Chipmakers continue to migrate to the next node, but there are signs that traditional IC scaling is slowing down.

So what’s causing the slowdown? Or for that matter, what could ultimately undo Moore’s Law?

It could be a combination of factors. To be sure, IC design costs and complexity are soaring at each node. Scaling challenges are also playing a role. And overlay—a little-known and arcane part of the flow—could also slow or halt the train.

Today’s chips have multiple layers. In simple terms, overlay is the ability of a lithography scanner to align and print the various layers accurately on top of each other.

The overlay accuracies for today’s 193nm immersion scanners are measured in the single-digit nanometer range. At those tiny dimensions, overlay errors can occur in the flow, thereby impacting chip performance and yield. And as chipmakers move to multiple patterning, overlay becomes even more challenging. Aligning the various layers and masks is a daunting task.

“This could be a potential showstopper,” said Alok Vaid, deputy director and senior manager of advanced module engineering at GlobalFoundries. “The problem statement is as follows: You have too many layers that you want to align. The number of layers you have to align is increasing exponentially because of multi-patterning. And if you look at any of the logic company’s most advanced 10nm backend layer, there are up to 16 different masks for one layer. We are doing eight today for 14nm.”

In fact, the number of 193nm immersion layers is increasing by 50% from the 2xnm to the 1xnm nodes, according to ASML. The number of overlay metrology steps is increasing by nearly 100% at those nodes, the company says.

To address the problem, chipmakers require tighter overlay specs on the lithography scanner. IC vendors also require a new class of overlay metrology tools. And the tools themselves must work in unison in the fab with an acceptable cost-of-ownership (COO).

The industry is making various breakthroughs in all three areas, but is it enough to bring down the COO for the 14nm node and beyond?

Scanner challenges
Basically, the overlay and alignment function takes place in the lithography scanner. In simple terms, overlay is accomplished by adjusting both the wafer stage position and the reticle stage position using alignment marks on the wafer and the reticle. This is repeated perhaps 100 times to expose one mask layer on one wafer.

“Roughly speaking, overlay accuracy is generally around one-third of the feature size, more or less,” said Hamid Zarringhalam, executive vice president at Nikon. “So at 130nm, single machine overlay was around 40nm. When you consider scanners targeted for 20nm technology and beyond, requirements were on the order of 6nm for mix-and-match overlay. And now, for sub-10nm scanner applications mix-and-match overlay is on the order of 2.5nm. So in just a few years, the overlay has been cut in half.”

On top of that, there are more challenges. “Overlay on these small patterns has become of prime importance, especially when multiple patterning is employed,” Zarringhalam said. “Challenges for tool makers will be to continue to reduce overlay error below its already impressive values. Challenges for chip designers and EDA vendors will be to come up with designs more impervious to overlay error, and to use process methods that are self-aligned or even self-correcting. A challenge for everyone is to remember that overlay is only one part of the more general edge-placement error, to which OPC/EDA and process effects also contribute significantly.”

Overlay errors can occur in the scanner and elsewhere in the fab flow. “Some think that overlay is only a lithography problem. It’s not. It’s an accumulative effect,” said Shibu Gangadharan, senior director of marketing at Applied Materials. “The scanner and mask contribute to it. How you measure contributes to it. And films and processes contribute to it. Films and processes also add stress on the wafer. And that will impact how your image gets transferred.”

Metrology challenges
For that reason, chipmakers must conduct a plethora of overlay measurements on the wafer in the flow. At 14nm and beyond, multiple patterning reduces the tolerable overlay error to only a few nanometers.

In overlay metrology, there are two main tool suppliers—ASML and KLA-Tencor. ASML is known for in-line tools, while KLA-Tencor sells standalone systems. Both vendors provide tools using scatterometry, which is an optical critical-dimension (OCD) technique that measures the changes in the intensity of light.

Generally, the tools must have three attributes. “We need accuracy. We need lots of measurements at high speed. And they have to align somehow,” GlobalFoundries’ Vaid said. “We’ve got to do these three things all together. Otherwise, overlay is a showstopper.”

Today’s tools are doing the job, but there is a gap. Each tool vendor has its own proprietary accuracy spec. What’s missing is a standard reference accuracy spec. “There is a gap in reference metrology,” Vaid said. “We don’t know if what we are measuring is correct or not, because there is no reference metrology.”

Suppliers of CD-SEMs are trying to devise a reference metrology spec, but the data is limited. So as before, chipmakers must rely on a toolmaker’s own reference data for accuracy purposes. “We are accomplishing this by using the accuracy flags, or self-validation from each supplier,” Vaid said.

On the other hand, tool vendors are moving on the accuracy front in other respects. Typically, the tool doesn’t conduct measurements on the actual device, but rather on small objects called targets. Targets are pre-fabricated, diffraction-based structures. In simple terms, the target mimics the behavior of the device.

ASML, for one, uses simulation software to design its targets for a given patterning application. This, in turn, helps enable the development of a target with a tight accuracy spec, according to Kaustuve Bhattacharyya, a technical director from ASML, in a recent paper.

The targets themselves are also moving in a new direction. If traditional targets are used at the 1xnm node, metrology tool costs, and measurement times, could spike, according to ASML.

So, ASML and KLA-Tencor are both moving toward multi-layer targets for the multi-patterning era. Multi-layer targets enable multiple measurements in a single acquisition, thereby reducing cost and measurement times.

Recently, KLA-Tencor rolled out the Archer 500LCM, an optical overlay metrology system. Offering both imaging and laser-based scatterometry measurement technologies, the Archer 500LCM supports a diverse range of overlay measurement target designs, including in-die, small ditch and multi-layer. This enables accurate overlay error measurement for different process layers, device types, design nodes and patterning technologies.

“If you monitored all of these inter-relationships with targets one or two years ago, you would need 15 separate targets. You would have to put them on the scribe line, and try to map out all of those interactions,” said Brian Trafas, chief marketing officer at KLA-Tencor. “We have made a single multi-layer target that is able to make all of those measurements. We have target designs that can help with multiple pattering. We can actually put them in-die.”

In-die metrology is a key enabler. It puts the targets on the actual device, which enables better correlations between the various measurements. In many cases, though, the targets are still outside the device and located in the scribe line. The measurements between the scribe and the actual devices are supposed to match, but the correlations are starting to break down amid the migration towards more complex devices like finFETs and 3D NAND.

Fab integration
Now, here comes the next hard part. The scanner, metrology tools and other systems must work together in the fab. “Every nanometer matters. We see 2D going to 3D. We see very tight CD and overlay budgets within litho. Then, there’s shrinking process windows in the fab,” Trafas said. “When we break down the sources of errors, there are traditional litho errors, overlay errors and scanner CD errors. And within the litho process itself, there may be process variations. And then, there are other sources of errors in the fab.”

At SEMI’s recent ASMC event, GlobalFoundries and KLA-Tencor presented a paper that described a way to bring more efficient overlay into the fab. This method uses a corrections-per-exposure (CPE) and a run-to-run (R2R) overlay control technology throughout the fab.

In the fab, chipmakers may have three basic and independent control loops for the overlay function–automated process control (APC); CPE; and a scanner baseline control loop, according to GlobalFoundries and KLA-Tencor.

Basically, APC is the central system or controller that determines the operation of the tools and other functions in a fab. One APC technique, called R2R, enables the modification of the processing parameters between the tools.

CPE, which is a separate control loop from APC, improves the overlay within the entire fab flow. This static CPE loop is implemented once per device and layer, according to GlobalFoundries and KLA-Tencor. Then, the scanner loop corrects the mechanical and optical drifts within the scanner.

Basically, in the fab, the three control loops—APC, CPE, and the scanner loop—independently transmit data back and forth into the scanner, metrology tools and other gear.

This methodology, however, is inefficient and time consuming. It could involve 1,100 separate measurements on the wafer alone, according to Lokesh Subramany, a principal process engineer at GlobalFoundries. “Any drift or sudden shift in tool signature between two CPE update periods can cause worse on-product overlay and a higher rework rate. Or even worse, (it could) lead to yield loss at the end of the line,” Subramany said.

To solve the problem, GlobalFoundries and KLA-Tencor described a new methodology, where the three control loops are integrated into a single system. APC, CPE and the scanner loop would still exist, but they would transmit data to a central “converter and combiner” mechanism.

This mechanism, in turn, would transmit data to the tools in one control path. “This basically means you are correcting each and every exposure while printing,” GlobalFoundries’ Vaid said.

All told, the methodology allows chipmakers to make fewer but more efficient measurements across the wafer. It also enables an improvement of up to 20% in term of on-product overlay on several critical layers at 28nm and 14nm, according to GlobalFoundries and KLA-Tencor.