Reducing The Tapeout Crunch With Signoff Confidence

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Progress is being made in automated fixes during P&R, but most solutions rely on proprietary verification decks.

Crunch time—that last six to eight weeks before tapeout. There’s always too much to do, and too little time. No one wants problems at this stage, because problems mean changes, and changes mean delays. At leading-edge nodes, however, we’re running into some new problems that need new solutions.

We all know design rule numbers and complexity are going through the roof as we try to use 193nm lithography to create designs at 40nm and below (Figure 1). Digital IC implementation flows always have relied on a certain level of abstraction during place and route (P&R) to convert schematics to layouts in a reasonable turnaround time. Typically, a router uses a tech file, a set of simplified design rule checking (DRC) and design for manufacturing (DFM) models, to provide the optimal tradeoff between runtime and accuracy during routing. Once the implementation is complete, the GDSII layout is verified using signoff-quality DRC/DFM models and Standard Verification Rule Format (SVRF) rule decks. This process works as long as the number of violations discovered at signoff is relatively low. However, at advanced nodes, there can be hundreds, or even thousands, of DRC/DFM violations.

CA_SemiMD_Reducing_Tapeout_Fig1_Design_Rules
Figure 1. At advanced nodes, design rules are expanding significantly in both the total number of rules, and the complexity of individual rules (operations).

Additionally, there is always a gap between the rules used during P&R in the form of a tech file and those in the signoff rule deck. As a new process node matures, the foundry’s design rule files are constantly updated to address manufacturing issues as they are discovered. It stands to reason that these foundry signoff decks are intrinsically the most accurate and complete representation of actual manufacturing requirements. The rules used by the P&R system, expressed in LEF or similar syntax, are simpler, and frequently fall out of sync with the foundry rules. In addition, at 28nm and below, there are some rules that simply cannot be expressed in the simpler LEF or tech file Tcl-like language. As a result, the router can report the layout to be DRC/DFM clean, but signoff analysis can still find a large number of violations.

Another challenge is the turnaround time of the P&R process at advanced nodes. Designers are finding that changes needed to meet stringent DFM requirements are starting to affect traditional design metrics like timing, power, and signal integrity. All IC designers know that using any router with all the signal integrity checking turned on means the router takes forever to converge. So designers routinely turn off signal integrity checking, to go as fast as possible to complete routing, knowing they will have some issues to resolve afterwards. They can accept a reasonable level of rework in return for working with an abstraction to get an acceptable turnaround time, but at advanced nodes, “reasonable” is proving to equal “impossible.”

At 40nm and below (Figure 2), there are many complex rules for how vias are created and connected. For example, there are now many via types (shapes) that must be used in the correct situations, and many rules for how they are enclosed (surrounded) by the connecting wires to ensure a reliable electrical connection. In fact, there are so many rules, and so many types of vias, it is hard for a P&R tech file to capture all of them. If the P&R system cannot recognize via errors, how can it fix them?

CA_SemiMD_Reducing_Tapeout_Fig2_Metal-Via_Rules
Figure 2. Beginning at 40nm, the number of design rules for vias and metal layers began increasing at a substantial rate, reflecting the complexity of manufacturing at advanced nodes.

The lack of automated functions for repairing these DRC/DFM violations during P&R is slowing the design process at advanced nodes. At best, the changes needed to fix signoff errors add significantly to the tapeout timeline—at 28nm, it takes an average of 20 minutes to repair each DRC/DFM violation, growing to 40 minutes at 20nm. At worst, they can lead to new manufacturing violations, or negatively impact the performance targets of the design, requiring even more rework, followed by additional extraction and timing analysis. In short, the design-then-verify flow that has worked in the past can become increasingly unmanageable and unpredictable.

In a similar way, P&R systems rely on an abstract view of cell libraries and other IP during the placing and routing process. The router is simply making connections to a cell’s input and output points, so it is not aware of any layout violations that may occur due to the cell’s internal layout, or due to boundary conditions with the surrounding layout. When designers run the signoff DRC tool, which views everything via the real physical GDS description, they suddenly see many violations that were not apparent before. When the signoff DRC tool flags a violation on a block of IP, the P&R system is very limited in its ability to fix that error, because it only has access to the abstract view.

Routing deals with cell placement, power and ground routing, signal routing, and clock tree synthesis (CTS). Defining all the signal routing is what most of us call final or detailed routing—this phase of the process is all about the P&R tool’s capacity and turnaround time. Although a high amount of automation is provided by P&R tools for signal routing, power and ground routing is much more like custom layout from the designer’s perspective, because there are many design issues, such as IR drop, current inrush, and electromigration (EM) issues, that require the designer to “tweak” the power grid layout provided by the P&R tool. Clocking in a complex SoC is at the heart of performance and power consumption. During the clock tree synthesis (CTS) process, the router must optimize skew, buffering, and many other factors across the entire layout. Making any modifications to the layout of clock connections is very complicated, and carries a high risk of “ripple effects,” so designers must be very cautious and careful when making these changes. Unfortunately, very limited automation exists to help designers with these P&R issues.

The general solution to these routing problems is to perform signoff-quality DRC of these sensitive parts of the design as early as possible in the flow, so all violations can be identified before they cause more expensive ripple effects further down the line. But just identifying the violations early is not enough—there are still far too many issues to fix manually if designers want to maintain development schedules. Designers also need tools that can implement customized fix options correlated to the type of topology that is being selected and used for power/ground and clock tree creation, because any modification to a power/ground special route will have an impact on IR drop and EM.

So what are our options? Progress is being made in providing automated fixing capabilities during P&R, but the current downside is that most of the solutions rely on their own proprietary verification decks, rather than the foundry-supplied signoff DRC and DFM decks. Without access to signoff decks, the question is whether these solutions can provide adequate coverage for today’s complex designs, as well as what’s coming. With manufacturing requirements such as double and triple patterning compliance being added to the design rule decks, and an increasing significance being placed on circuit reliability and power usage, designers will continue to look for ways to complete P&R with a design that is signoff DRC-clean and implements the optimal configurations and circuitry demanded by today’s markets.




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