SEMICON West Preview: Test

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Test sector changes with maturing IC industry, including free testers with software subscription, payment by PayPal, design standards for board-level security.

Talking with the speakers scheduled to speak in the programs on IC testing at SEMICON West this year, I was struck by how much this equipment sector is changing as the value moves to software and the cloud. It has to be the first time I’ve ever mentioned PayPal in the same paragraph with semiconductor equipment, to say nothing of the business model of free hardware with software subscription.

Almost everything about how Advantest is promoting its testers for design verification differs from the usual semiconductor equipment business model. Instead of customers developing their own custom software to run on the hardware it sells, Advantest is supplying its own standard cloud-based verification test software — and supplying the tester hardware free with the software subscription. The same test equipment can be used to test either logic or memory, by re-configuring the firmware in the system. The testers and product-specific software can be ordered online, the hardware shipped overnight, the software downloaded. “It will be just like buying from Amazon. You can even pay with PayPal.” says A.T. Sivaram, CTS business development manager at Advantest America, who will speak in the Design for Test program at SEMICON West 2014.

“There is an attitude of “why fix it when it isn’t broken,” but a lot of testing is actually much the same, so using the ready-made standard software and just configuring the flow as needed can reduce the cycle time for design verification from six weeks to just two,” Sivaram notes. “Now that the industry is becoming more mature, it’s possible to use a cheaper and faster product.”

The company is going to a pay-by-the-month system, so the software can be paid for only when it’s needed for the intense phase of testing to verify the design. Sivaram notes that since verification testing is concentrated in the two to three months after “first silicon” comes back from the fab, smaller companies can save by paying for the software in the cloud only when they need it. Some options for customization are possible for companies who find the standard IP is not exactly what they need. “We want people taping out two to three designs a year to be able to do six, and that would also mean more use for our systems and a consistent revenue stream,” he says.

Smarter design-for-test now means need for design-for-security, as well
All the sophisticated advances in design-for-test and test equipment that can see so well into the inner workings of the chip also ironically now mean the test port can be a gaping “back door” security hole into the core IP and even into the personal data stored in the system’s memory. These tools enable access into what’s going on inside chips and on boards and give resolution to firmware, therefore, creating a potential security vulnerability. “The system firmware (memory contents, Flash, programmable devices) is one of the hardest test problems, so testing provides the most resolution there by extracting a lot of information from the test port, but that’s also a way others could suck out a lot of data, likely the very information that the system maker most wants to keep secure,” says Al Crouch, chief technologist, Embedded instruments and IJTAG, at ASSET Intertech, who will speak at the Test Vision 2020 program.

Crouch notes that it’s easy enough to add custom security to particular chips, and many companies do, but systems makers have a tougher problem securing their boards, with all the different chips using different security systems or sometimes none at all. “They need to track which chip is used where and which keys and codes go with which of all these chips,” he says. Work with Southern Methodist University has developed a “standardizable” JTAG lock and key system that takes up little chip real estate and adds only 1.1ms to test time for a 48 key system added to a 5120 bit scan path, which researchers calculate should take 9,148 years to break. System makers — who may be using chips from 16 different companies on boards assembled by three suppliers —would like any standard security system to be a fully portable plug-and-play solution that could be used across the board. IEEE is starting to investigate interest in such a standard.

Pros and cons of custom in-house testers vs. off-the-shelf models
The Test Vision 2020 program also features a debate on the pros and cons of “make vs. buy.” The panel will consist of test equipment designers from device makers and outsource test houses along with ATE companies and third-party integrators who build test equipment and supply to the industry— including Advantest, Altera, Amkor, KYEC, National Instruments and Texas Instruments, plus a moderator from Teradyne.

Testing more devices in parallel can bring down the cost of test, but the cost model is changing further as suppliers are adding more value to meet customer requirements. Users can build their own equipment to focus on exactly what they need, without spending on “extra capabilities.” However, it challenges the traditional cost models as they need to own all aspects of manufacturing integration and keep up with the waves of innovation. This includes: occasional fleet upgrades and designing equipment that’s not only easy to learn and maintain, but also easy to use and improve (with sophisticated development & debug tools).

“We pick people who will speak out, and our audiences are never shy to speak up as well” says Steve Tilden, director, Markets & Technologies at Xcerra Corp. (formerly LTX-Credence), who is vice general chair of the program. “So the Test Vision panel should be lively.”

For more information on SEMICON West, visit: http://www.semiconwest.org. For Test programs, visit: http://www.semiconwest.org/SessionsEvents/Test




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