One Flow To Rule Them All


The new mantra of shift left within EDA is nothing new and first made an appearance more than a decade ago. At that time there was a very large divide between logic synthesis and place and route. As wire delays became more important, timing closure became increasingly difficult with a logic synthesis flow that did not take that into account. The tools subsequently became tied much closer togeth... » read more

Ensuring Optimal Performance For Physical Verification


By accessing the most recently qualified version of foundry rule files, users get the most efficient rule implementations. By adopting the most recent version of Calibre, users get the latest improvements in available operations, operation performance, data hierarchy optimization and total scaling, providing the best possible performance and minimizing runtimes. Design teams running full-chip D... » read more

Incremental Design Methodologies


There are times when we become stuck in the past, or choose to believe something that is no longer true or actually never was true. As we get older, we are all guilty of that. History tends to rewrite itself, especially given that this industry is aging. One of these situations occurred recently, and comments from an industry luminary didn’t align with the thoughts and memories of other peopl... » read more

The Route To Faster Physical Verification And Better Designs


By Nancy Nguyen & Jean-Marie Brunet As we’ve moved to today’s leading-edge nodes, physical layout designers have faced more and more challenges to get their design to tape-out on schedule. Timing becomes increasingly difficult to converge, power reduction for both IR and leakage becomes a big issue, and most importantly, how do we meet all of the ever-growing and more complex signoff d... » read more

Signoff Intensity On The Rise


By Ann Steffora Mutschler and Ed Sperling Lithography and signoff are crossing swords at 16/14nm and 10nm, creating new problems that raise questions about just how confident design teams will be when they sign off before tapeout — and how many respins are likely to follow. While designs at 20nm, 16nm and 14nm typically rely on colorless double patterning, at 10nm colors are mandatory. ... » read more

Reducing IC Cycle Time With Calibre


Technology is both a blessing and a curse. The same shrinking of transistor size that has enabled chip designers to place significantly more functionality on the same die area is also responsible for the significant increases we have seen in the number and complexity of verification rules. It would be nice if we could use this phenomenon to our advantage, as an excuse for why our job of physica... » read more