tag: signoff

The Seven Steps Of Formal Signoff
By Iain Singleton - 28 May, 2020 - Comments: 0

“Signoff” may be the most exciting—and frightening—word in semiconductor development. After many months, or even years of team effort, committing a design to silicon fabrication is indeed an exciting and rewarding event. But, there’s often significant anxiety involved as well – if any missed issues result in having to “turn” the chip, the increased costs and time-to-market delay... » read more

Verification At 7/5nm
By Ed Sperling - 25 Apr, 2019 - Comments: 0

Christen Decoin, senior director of business development at Synopsys, talks about what’s missing in verification, how is that affected by complex chips such as 7nm SoCs or AI chips, and why more steps need to be done concurrently. https://youtu.be/bz6KyJh67sI » read more

How Qualcomm Got Faster Signoff DRC Convergence
By Srinivas Velivala - 28 Mar, 2019 - Comments: 0

Qualcomm Incorporated designs and markets wireless telecommunications products and services that are the foundational technologies that others build upon, from mobile processors to embedded platforms, Bluetooth products, and cellular modems. In the fast-moving mobile phone market in which Qualcomm competes, companies who can get to market more quickly gain a strong competitive advantage, along ... » read more

MISing In Signoff
By Jim McCanny - 31 Jan, 2019 - Comments: 0

Timing signoff is critical to ensure your design will perform as expected before it is taped out. For many designs, signoff and subsequent ECOs are focused on the performance target and iterating to meet that.  Once the performance goals are met then the attention passes onto hold-time fixing and then, usually, quickly onto tapeout.  However, even after extensive signoff analysis, silicon fai... » read more

The Impact of Domain Crossing on Safety
By Brian Bailey - 31 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Reliability, Machine Learning And Advanced Packaging
By Ed Sperling - 11 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss reliability, resilience, machine learning and advanced packaging with Rahul Goyal, vice president in the technology and manufacturing group at Intel; Rob Aitken, R&D fellow at Arm; John Lee, vice president and general manager of the semiconductor business unit at ANSYS; and Lluis Paris, director of IP portfolio marketing at TSMC. What follows ar... » read more

So Many Waivers Hiding Issues
By Brian Bailey - 05 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Beyond Signoff
By Annapoorna Krishnaswamy - 14 Jun, 2018 - Comments: 0

The future of connectivity is very promising - the new era of semiconductors will give rise to transformational products that will enable seamless connectivity with 5G, smarter devices with AI, next generation mobility with autonomous vehicles and immersive experiences with AR and VR. These cutting-edge electronics systems will require the use of advanced sub-16nm SoCs and complex packaging tec... » read more

Timing Signoff Methodology For eFPGA
By Geoff Tate - 03 May, 2018 - Comments: 0

An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells. The timing signoff for an eFPGA’s interface with the rest of the chip is designed to leverage standard ASIC timing signoff flow for a hard-macro: as long as inputs/output to/from the eFPGA are all flopped, the int... » read more

8 Checks That Every PCB Designer Needs To Achieve Electrical Sign-Off
By Mentor, a Siemens Business - 25 Apr, 2018 - Comments: 0

Automate electrical design rule checking (DRC) for fast, cost-effective PCB design verification. These eight rules apply regardless of your PCB layout tool or level of expertise. To read more, click here. » read more

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