2.5D Adds Test Challenges

OSATs and ATE vendors are making progress in determining what works and what doesn’t in 2.5D packaging, expanding their knowledge base as this evolves into a mainstream technology.

A 2.5D package generally includes an ASIC connected to a stack of memory chips—usually high-bandwidth memory—using an interposer or some type of silicon bridge technology. It’s different than a full 3D-IC package, where memory or logic are stacked directly on logic, tied together with through-silicon vias drilled through the middle of those chips.

Most experts believe that full 3D packaging is at least five years away from mainstream deployment. 2.5D, in contrast, already has made inroads in markets where price sensitivity is low and demand for throughput to memory is extremely high, such as networking, server and graphics applications.

Fig. 1: AMD’s Fiji chip. Source: TechSearch International

“The current 2.5D architecture has a lot to do with memory,” said Calvin Cheung, vice president of engineering and business development at ASE. “As you know, the memories are very expensive. A lot of our customers have spent a lot of time on this area. The initial solution was, do it one step at a time. In other words, involve an ASIC on the silicon interposer before you put the memory on. The memory stacks are expensive, especially the first generation. Interposers are very straightforward.”

HBM costs are expected to drop, though, now that both Samsung and SK Hynix are shipping it in volume. Both companies discussed a new generation of that memory at Hot Chips last summer, which is expected to be denser with a lower core voltage—and presumably cheaper.

“You see people using HBM in a more flexible way,” Cheung said. “2.5D has picked up a lot of traction. Right now, everyone is focused on a lot of the cost options. It’s for logic and a processor that require memory close to the ASIC. These days 2.5D is pretty much the network controller and a mixture of HBM.”

Graphics processing units and network processors are leading applications for 2.5D packaging, according to Cheung. “The processor is getting bigger. You need a lot of memory to feed the processor. You also want that memory close to the processor.”

CPUs can be “power-hungry and dominant,” Cheung noted. “There’s a lot of heat dissipation and management that people need to overcome. You have one chip that is much hotter than the other chips. How do you manage the power dissipation?”

Power dissipation has been particularly problematic for 3D-ICs. There is no easy way to remove the resulting heat, and often it’s even difficult to determine where thermal hotspots will show up because heat can migrate on the silicon. That makes testing essential, but with 3D-ICs there is no simple way to do that. Once they are packaged, the chips inside that package are inaccessible to the tester.

With 2.5D, test is less circuitous, which is a key reason why this technology has seen more rapid adoption. Known good die, production testers, software, and other factors are easing the challenges of 2.5D chip testing, according to Cheung. “We’re in pretty good shape. The 2.5D process is becoming much more mature. People are not so worried about, ‘My HBM cost me 50 bucks, I put it on the interposer, and it failed and I have to throw away this ASIC.’”

Interposer testing
Not everything is so simple in 2.5D, though.

“The biggest challenge is the interposer having a thin die,” said Ram Praturu, director of test product technology marketing at STATS ChipPAC. “In a 2D [chip], basically you’re testing the package, and in a single package you test the whole IC. The accessible pitches on the 2D are pretty straightforward. On the 2.5D, everything is downsized. You have an interposer and TSVs come in. You have to treat that as a known good interposer, or at least one that’s known to be pretty good. You try and test it before you send it down. The difference is that with 2.5D, you have the additional step of handling the interposer. How do you want to test that on the substrate or on the die?”

The interposer already has been tested by the supplier, but it’s still the biggest unknown.

“The die can be tested at the wafer level or the die level, Praturu said. “You can get known good die. That is a mechanical structure. The biggest challenge is, do you want to test it at speed? If you want to test it at speed, you start assembling these things. For whatever temperature, does this dissipate? What is the power dissipation? You have to take that into account. Do you want to test one chip at a time, or do you want to assemble everything? If you have multiple die and one of them goes bad, the whole thing goes bad. There could be three or four die, with interposer and substrate, and that could be pretty expensive.”

Assembly and test contractors must figure what is on each of these die, and then decide whether to put it on an ATE or to use a system-level test, he said.

STATS is still handling relatively low volume in testing 2.5D chips. The company started seeing 2.5D chips about three years ago. “Processors and memory combined, and then some logic also added to that. Those are the kind of chips we’re seeing right now,” Praturu said.

STATS has not begun working with 3D-ICs yet. It has the technology to do it, but so far there is no demand. System-in-package, meanwhile, is underway using with multiple die, but there is “very little” activity with TSVs, he said.

With this advanced packaging, the big issue is “handling the test – how do you touch it, how do you probe it?” Praturu said. “The fine pitch of these 2.5D die, wafer-level die, and interposers that go down to about 20 to 30 microns, that was a problem for probing.”

Gerard John, senior director of advanced test at Amkor Technology, identified similar concerns. “It starts off with, ‘Should we start testing the interposer?’ The main thing in 2.5D is using an interposer structure, typically a silicon interposer that has through-silicon vias. When these interposers come into an OSAT, it’s made by a fab. They created through-silicon vias. The wafers are still about 800 microns thick, the TSVs about 100 microns in length, and the TSVs are only exposed on one side. Therefore, it’s not possible for the fab to verify the electrical connectivity between the top and the bottom side of the wafer. Essentially what happens is they do some optical inspections at the fab and declare the wafer good enough to be shipped to the OSAT before the processing.”

Fig. 2: Xilinx 2.5D chip with interposer. Source: Xilinx

But there are lingering questions about whether and how to test the interposers.

“If you look at the back side of the interposer, on the front side of the interposer it’s only about 25 microns,” said John. “On the back side, it’s about 80 microns in diameter. So, it’s a lot easier to probe the back side of the wafer, and this can only be done after the back-grinding process at the OSAT. We did an extensive study here at Amkor. In the process of qualifying a TSV vendor we ran a lot of experiments, and one of these was to see the quality of TSVs. In order to test connectivity from top to bottom, we really needed a double-sided prober. That was one of the big challenges. Double-sided probers are not mainstream in OSATs. These are one-of-a-kind machines, really expensive, about four times the cost of a standard prober, and it’s got only one purpose, namely using it for TSV testing. The industry hasn’t caught up to doing double-sided probing. Typically, what they’re doing right now is using daisy chains that go from the front side of the wafer to the back side.”

Amkor customers have had to compromise on test structures for 2.5D packages. One path is using “some sort of redundancy for the TSVs,” John said. “From our experience, we have seen that once you have redundancy, and a better-qualified process is mature, you don’t need to critically test interposers anymore.”

Another issue is the thinness of wafers following back-grinding. “You need to have special handlers that can pick up these wafers and move it to a probe or a probing station, so in order to avoid that, we tried to go with wafers that are in glass carriers, or some sort of carrier, a carrier support system,” John said. With the carriers, the interposer die can go on existing standard probers. “At the end of the day, it’s all about added costs in test that make the product more expensive—and keeping it down for a product to get past that ‘too expensive to build’ or even worth it.”

After interposer testing, there’s attaching the die to a substrate. An ASIC has to be tested at speed. Most 2.5D packages involve an ASIC or a processor, plus memory chips. Functional testing of a partially assembled package is done, followed by system-level testing, and final test with ATE.

The challenge in system-level testing is it takes a long time, which is why parallel testing is being deployed. But just as in the wafer sort process, there is a lot of heat dissipated, so thermal control is required.

“The test process is a long chain of events,” John explained. “Does it make sense to test at all these points?” OSATs and their customers have to balance scrapping cost against testing cost.

The form factor
For Amkor, 2.5D chips represent a small but growing business, John said. The company has been dealing with 2.5D packaging for about two years. “Essentially, we’re trying to reduce the power per bit. So, your devices are going to be low-power devices, but high performance. You can look at 2.5D in applications that require low power, but still require the higher performance. And with form factor, you’re saving a lot of real estate on the board by shrinking everything, putting it on a substrate. Lines and spaces are fine, so you can make things more compact, and in a smaller area you can provide more processing power, along with memory. Those are the typical application spaces for 2.5D.”

Andreas Nagy, Xcerra’s senior director of marketing, argues that it always begins with form factor, but adds that testing isn’t that much different with 2.5D. “Most of the 2.5D packages are pretty similar to 2D packages in terms of how to test them,” he said.

Nagy has some experience in 3D packaging with microelectromechanical system (MEMS) devices. Some MEMS chips need to be encapsulated and hermetically sealed to the outside world to retain the gas inside the 3D structure. “We do not see a difference from traditional MEMS devices,” he added.

That said, because of the challenges in 3D assembly and test, “the cost is getting higher and higher,” Nagy said. “Even with known good die, failure means scrapping all the die.”

The Xcerra executive points to Taiwan Semiconductor Manufacturing’s testing in the chip-on-wafer-on substrate process. Partial stack testing can be done during assembly, he said.

Conclusion
OSATs seem to have a high level of confidence in testing 2.5D chips, given their experience with the technology. Some are pressing forward in handling and testing 3D-ICs, as well, but that is likely to be a much slower ramp.

In the short-term 2.5D will continue to be the packaging technology of choice for high-throughput, price-insensitive applications, particularly where a smaller form factor is required. But it likely will see some encroachment at the low end of that spectrum from fan-out wafer-level packaging, and sometime in the next few years from full 3D-IC, and in both of those markets ease of testing, and experience with testing methodologies, could have a significant impact on which packaging gets used and for which markets.

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