2D Semiconductors Make Progress, But Slowly

Researchers are looking at a variety of new materials at future nodes, but progress remains slow.

In recent years, 2D semiconductors have emerged as a leading potential solution to the problem of channel control in highly scaled transistors. As devices shrink, the channel thickness should shrink proportionally. Otherwise, the gate capacitance won’t be large enough to control the flow of current. Unfortunately, traps and other interface defects degrade carrier mobility and are proportionally more important in thin channels. The practical limit for silicon channel thickness appears to be about 3nm.

Two-dimensional transition metal dichalcogenides (TMDs), such as MoS₂ and WSe₂, are interesting because they have no out-of-plane dangling bonds, Stanford researcher Aravindh Kumar explained in an interview. Interactions at the top and bottom surfaces are limited and have little impact on carrier behavior. MoS₂, in particular, is easy to synthesize and very stable.

Still, TMD deposition typically requires very high temperatures, well above the tolerance of the bottom gate structures that are typically used. At Imec, for instance, research fellow Yuanyuan Shi and colleagues used a 1,000°C MOCVD process for MoS₂ deposition.[1] For this reason, most research on TMD devices uses either flakes exfoliated from bulk material, or freestanding layers grown on sapphire or silica and then transferred.

While layer transfer methods allow device research to proceed in parallel with process development, a low-temperature silicon-compatible deposition process is essential for commercialization of TMD devices. In work reported at December’s IEEE Electron Device Meeting, Intel senior staff research engineer Kevin O’Brien and his colleagues used pre-patterned metal oxide seed crystals to create nucleation sites for WS₂ growth. Placing the metal source directly on the wafer avoided the use of solid metal oxide CVD sources. Controlled nucleation restricted the location of TMD crystals, and therefore the grain boundaries associated with them.[2]

The quality of freestanding MoS₂ sheets depends on the deposition process and the original substrate. For example, in ACS Nano, research fellow Manoj Tripathi and colleagues at the University of Sussex reported that MoS₂ grown on silica substrates by CVD was in tension, as it contracted more than the silica during cooling.[3] The stored tension prevented formation of wrinkles, a common issue in exfoliated MoS₂.

Fig. 1: Crystal structure of a monolayer of transition metal dichalcogenide (a) side view, (b) top view. Source: 3113Ian at English Wikipedia.

Optimizing device structures
As a thin film grows, incoming molecules naturally assume the most energetically favorable configuration. In MoS₂, deposition directly on sapphire is only slightly more favorable than deposition on pre-existing MoS₂ surfaces. As a result, islands with multiple MoS₂ layers can form before the layer in contact with the substrate is complete. The edges of these islands do have dangling bonds, though making them more reactive. Shi’s Imec group exploited edge reactivity by using a post-deposition Cl₂ etch to preferentially remove growth islands. Island removal improved surface roughness and thickness uniformity in MOCVD films grown on sapphire.

Just as the future of silicon devices seems likely to depend on stacked nanosheets, TMD transistors are likely to need several stacked channels to carry enough current. Peking University professor Xiong Xiong and colleagues made stacked MoS₂ channels by transferring two large freestanding monolayers, then etching the material to the desired device size. The same process could also be used to make stacked complementary FETs, for instance using MoS₂ for NMOS and WSe₂ for PMOS in a single stack.[4]

As noted above, the best current MoS₂ devices depend on back gate designs, where the gate metal and gate oxide are deposited on a silicon substrate and then a MoS₂ layer is placed on top. This approach gives much better device performance, but ultimately top gate devices are more scalable. As in gate-all-around silicon transistors, dual gates with matching top and bottom capacitance will give better channel control than a single gate. Imec device integration engineer Xiangyu Wu and colleagues used a GdAlO_x interlayer to improve capacitance matching in dual-gate MoS₂ devices. The interlayer appears to reduce short channel effects and improve threshold voltage control.[5]

Processes to make freestanding MoS₂ films are now mature enough to produce statistically useful numbers of devices. Researchers are now reporting statistics for thousands of devices, a prerequisite for a scalable process. Unfortunately, those thousands of devices still lag behind silicon’s performance benchmarks. Contacts to TMDs are especially challenging.

Making contact
There appear to be two sources of contact resistance. Defect-induced gap states come from surface defects created either during MoS₂ deposition or during metal contact formation. Work at TSMC used oxygen to passivate sulfur vacancies, one source of defects, during deposition.[6] Kumar suggested that physical bombardment from thermally excited contact metals also contributes to contact resistance. The Stanford work used tin and indium, which are low melting point materials, allowing deposition with minimal damage. When capped with gold, these metals form alloys that are stable above 450°C, making them compatible with existing BEOL processes.[7]

Metal-induced gap states, the other contributor to contact resistance, lead to Fermi level pinning. When the Fermi level is pinned, the energy barrier height at the interface is independent of the contact metal’s work function, and cannot be used to tune the threshold voltage. Semimetals are interesting as potential contacts because they have no band gap and a low density of states at the Fermi level. As a result, they tend not to generate MIGS. Of the semimetals, bismuth and tin have low melting points, at 271.5°C and 231.9°C, respectively. Antimony, with a melting point of 630.6°C, is more process compatible. In work presented by TSMC, Ang-Sheng Chou suggested that alloying 40% antimony or more with bismuth could allow co-optimization of the contact barrier height, alloy conductivity, and melting point. For example, an alloy of 50% antimony with 50% bismuth gave a 540°C melting point with a barrier height of only 0.10 eV.[8]

While the Intel group’s best contacts also used antimony, they warned that MoS₂ NMOS devices lag well behind silicon benchmarks, with current 3x lower than silicon at target subthreshold swing values. For WSe₂ PMOS devices, the situation is even worse. Their best devices, using ruthenium contacts, achieved 50 μA/μm on current at a subthreshold swing of 141 mV/decade.

Most demonstrations of 2D semiconductor FETs use top contacts because they are easier to fabricate. Edge contacts are smaller, though, which can either reduce the overall device footprint or allow less aggressive scaling of the channel length. Moreover, as noted above, the edge of a 2D material does have dangling bonds. In contrast to the weak van der Waals bonds present in top contacts, edge contacts can potentially form a covalent bond. Terry Hung of TSMC, in work presented at the 2020 IEDM, showed that edge contacts eliminated Fermi level pinning.[9] The interface surface (an “interline” at the edge of a 2D material) forms a dipole, the effect of which decays rapidly with distance.

Conclusion
Overall, the outlook for 2D semiconductor devices is mixed at best. While recent research shows significant progress in both material growth and contact fabrication, devices that can plausibly compete with leading edge silicon have not yet been demonstrated. When and if they do emerge, they are likely to involve materials and processes that are alien to current fabs.

References
[1] Yuanyuan Shi et al.,”Superior electrostatic control in uniform monolayer MoS2 scaled transistors via in-situ surface smoothening,” 2021 IEEE International Electron Devices Meeting, 2021, pp. 37.1.1-37.1.4
[2] K. P. O’Brien et al., “Advancing 2D Monolayer CMOS Through Contact,
Channel and Interface Engineering,” 2021 IEDM, 2021, pp. 7.1.1-7.1.4
[3] Manoj Tripathi et al., “Structural Defects Modulate Electronic and Nanomechanical Properties of 2D Materials,” ACS Nano 2021 15 (2), 2520-2531
DOI: 10.1021/acsnano.0c06701
[4] Xiong Xiong et al., “Demonstration of Vertically-stacked CVD Monolayer Channels: MoS₂ Nanosheets GAA-FET
with Ion>700 μA/μm and MoS₂2/WSe₂ CFET,” IEDM 2021, 2021, pp.7.5.1-7.5.4
[5] Xiangyu Wu, et al., “Dual gate synthetic MoS₂ MOSFETs with 4.56μF/cm2 channel capacitance, 320μS/μm Gm and 420 μA/ μm Id at 1V Vd/100nm Lg,” IEDM 2021, 2021, pp. 7.4.1-7.4.4.
[6] Y. Lin, et al., “Contact Engineering for High-Performance N-Type 2D Semiconductor Transistors,” IEDM 2021, 2021, pp. 37.2.1-37.2.4
[7]Aravindh Kumar et al., “Sub-200 Ω·µm Alloyed Contacts to Synthetic Monolayer MoS2”, IEDM 2021, 2021, pp. 7.3.1-7.3.4
[8] Ang-Sheng Chou, et al., “Antimony Semimetal Contact with Enhanced Thermal Stability for High Performance 2D Electronics,” IEDM 2021, 2021, pp. 7.2.1-7.2.4
[9] T.Y.T. Hung et al., “Pinning-Free Edge Contact Monolayer MoS₂ FET,” 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 3.3.1-3.3.4, doi: 10.1109/IEDM13553.2020.9372028.