Big Changes In Tiny Interconnects

One of the fundamental components of a semiconductor, the interconnect, is undergoing radical changes as chips scale below 7nm.

Some of the most pronounced shifts are occurring at the lowest metal layers. As more and smaller transistors are packed onto a die, and as more data is processed and moved both on and off a chip or across a package, the materials used to make those interconnects, the structures themselves, and the entire approach for utilizing those structures is changing.

At the most fundamental level, the challenge is ensuring a good connection between different layers. The problem is that copper, which has been used been used for those interconnects since 130nm, has largely run out of steam. So at 10nm, Intel made a switch. The local interconnect layers—M0 and M1—incorporate cobalt, not copper, as in previous technologies. The remaining layers use traditional copper metal. Others are exploring the idea.

Generally, copper is still used for the other and traditional backend-of-the-line (BEOL) layers. Cobalt is mainly used for the liners here, although ruthenium is gaining steam. Other materials are also being explored as well as a newer technology called buried power rails.

“There are some really interesting interconnect developments, including the use of different materials and deposition techniques for those materials,” said David Fried, vice president of computational products at Lam Research/Coventor. “This includes thinner liners, barriers and seed layers, along with more conformal deposition techniques. We are also seeing different metals with lower resistance being used, and different combinations of liners, barriers, seed and fill that end up with a lower aggregate resistance. There are also many developments ongoing with dielectrics and lowering the ‘K’ but keeping them mechanically stable. There is a tremendous amount of work on plating versus depositing versus CVD, and new materials and new process technologies are being applied to new materials.”

This is much more complicated than it sounds. One of the problems with copper is that at the most advanced nodes it can diffuse into surrounding materials. That requires a barrier layer, but as scaling continues to 5nm and 3nm, those barrier layers need to be thinner. But they also need to be conductive.

Most of these barrier layers are conformal man-made materials, and even depositing them with enough consistency has become problematic.

“You’re trying to put a barrier layer down at 1nm or 2nm, so for that film to be reliable it has to be very consistent,” said James Lamb, Corporate Technical Fellow at Brewer Science. “Any minor errors will cause dramatic effects. If that barrier is 1nm thick and you’re missing a few atoms in one spot, that’s no longer a barrier. That is being pushed to near perfection. You have to have that film with no voids or holes in it at the very extreme end of the nanoscale.”

Any aberration can impact reliability, and ultimately yield. “If you have a barrier film or insulators that are very thin, you still have to go through the thermal cycle,” said Lamb. “If you have variations, those become seeds for separation or causing reliability issues after 100,000 or 1 million cycles, for example. There will be thermal cycles in any device in operation. Seed points can cause a breakdown or a crack or migration. One of the reasons we have new metals is they are less prone to migration than copper. That’s one of the advantages of cobalt and ruthenium. But when copper first came in with the dual damascene process, that caused all sorts of issues, too. There were two big introductions. One was CMP, which was required to make the copper process work. At that point, it was a dirty process because you were smearing copper around on your wafer. You couldn’t let that contaminate the rest of the wafer because if you got copper in the oxide or silicon it would migrate, making the devices defective. So that had to be isolated from the whole process, which included barrier layers. Those are typically not very conductive. And that’s causing a problem now. The barrier layers cause enough resistance to be a problem once you start doing a shrink. That’s where cobalt and ruthenium fit in. They both limit any kind of migration, so they can act as barriers or as the primary conductors. Cobalt has been around for awhile. Ruthenium is pretty new.”

Other options include molybdenum and nickel, as well as some alloys.

Introducing any new material into manufacturing is a slow process. Foundries are extremely conservative when it comes to making changes in their processes, and that conservatism has grown at each new node as prices rise, and as chips are used for longer periods of time in safety-critical applications such as automotive AI, or for mission-critical applications inside of hyperscale data centers.

“Every new material can cause a problem,” said Tomasz Brozek, senior fellow at PDF Solutions. “When people first started bringing cobalt into the backend-of-the-line for metallization, they started doing liners out of cobalt to improve reliability. But at the same time, the CMP wasn’t compatible. There was corrosion, dishing, and other effects you’d never see. It took a really long time to bring cobalt into interconnects. IBM was talking about cobalt for contacts for 10 to 15 years. But at that time there was really not a good reason for manufacturing with cobalt. Now, because of scaling, a tungsten contact is not just tungsten anymore — and the amount of tungsten that is in the contact holes is much smaller than it should be because of the liner requirements.”

Liners or no liners
Getting rid of liners would save an entire process step, but it also would have an impact on the overall design and, potentially, the overall reliability of these very expensive chips.

“Liners and barriers typically have high resistance,” said Brozek. “Everybody is looking for a new material that does not need liners, and this is what is driving new materials such as cobalt and ruthenium. For cobalt you still need a nucleation layer and a liner. For ruthenium, you could try to do barrier-less, or a liner that is a sputtered layer to grow the ruthenium. It may be possible to grow the ruthenium without a liner. Ruthenium is more resistive than copper, but if you take into account that you don’t need a barrier metal, that is actually better. Still, reliability has not been proven yet. It’s not clear how that will behave in all layout configurations. It’s easier to have straight lines and fill them with metal. You can say all your lines are straight and perfect. But can you afford zig-zags and two-directional patterning and fill that with metal. Will this new metal behave the same way? Will CMP behave the same way? All of that has to be investigated. And some of the failure modes only show up in mass production where you can observe tool reliability and worse corners and many other interesting things. Having a way of testing that in production, and after processing the chips, is a task the fabs are fighting.”

This also adds to the overall cost of a design, and not all companies working at the most advanced nodes see this as a necessary expense.

“The use of these interconnects is going to depend upon the application,” said Lam’s Fried. “You might see fragmentation by application out there for a few years. For high-reliability requirements, the liners, barriers, and seeds have to be absolutely perfect, so the industry will probably use more conventional materials for these applications. There will be other applications that don’t have the same reliability spec, and we might use more advanced interconnect materials to push a little bit harder on the thickness to obtain better performance. You’ll see things like ruthenium liners, or interconnects that use cobalt, molybdenum and other materials, including different dielectrics as well. You might be able to make more porous structures that sustain less mechanical stress and show improved capacitance. Research in this field is making great progress, and these new interconnect technologies are probably going to get implemented, but it may be very application-specific.”

Next-gen interconnects
New materials are only part of the strategy for interconnects. At Semicon Europe in 2019, Werner Boullart, manager of the plasma etch group at Imec, introduced buried power rails as a way of freeing up routing space at the local interconnects. These power rails are literally buried below “metal 0” in order to free up space.

Fig. 1: CFET with buried power rail. Source: Coventor

It’s well understood that transistors scale, but wires do not, which is why for some critical functions thicker wires are not uncommon. But at the most advanced nodes, there isn’t room for thicker wires. The result is higher resistance, which generates heat and increases IR drop. Burying the power rail moves that whole process from the middle-of-the-line to the front-end-of-the-line, according to Boullart, which in turn allows track height reduction while also allowing higher track height reduction.

According to Imec, ruthenium lines with an aspect ratio of up to 7 and a critical dimension of 18nm were used as a power rail, which was isolated at the FEOL in the oxidation process, rather than as a metal 1 layer. The result was low resistivity (8.8 µohms/cm). The research house also used a subtractive metal etch process for 12nm ruthenium lines with an aspect ratio of 3.8 and line resistance below 500 ohms/µm, which it has targeted for 3nm designs.

But there also are some riffs on this theme, which can have a significant impact on performance and density. In effect, this approach is like digging tunnels beneath the transistors. As Arm discovered, while working with Imec on this project, IR drop from buried ruthenium power rails with back-side power delivery was 7X better than buried power rails with front-side IR delivery. (The results are detailed in a paper presented at IEDM in December 2019.)

There were some surprises, however. Brian Cline, principal research engineer at Arm, said that using tap cells used to connect to the fins can end up being a placement blockage for other devices. “We also found that the design tools we use to develop these devices break in strange ways,” said Cline. “In particular, the tools didn’t recognize power rails running below metal 0.”

Conclusion
Interconnects at metal 1 and metal 0 are becoming a bottleneck for performance and a challenge for manufacturing, prompting foundries and research groups working at the most advanced nodes to utilize new materials, new approaches for routing signals, and entirely new schemes for how to manufacture these interconnects and where to place them.

But this is just one type of interconnect. As future stories will show, interconnects are more like a stack of different technologies, some operating at different levels of abstraction and with completely different properties and design parameters.

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