Removing The Accuracy And Time Tradeoff In EM Simulation
By Stephen Slater - 26 Mar, 2026 - Comments: 0

For years, electromagnetic simulation forced engineers to choose between accuracy and turnaround time. As simulation frequencies climbed beyond 60 GHz and designs became more complex, engineers could no longer avoid mesh refinement. Higher fidelity required more mesh elements in regions of high field strength. More elements produced larger sparse matrices. Larger matrices extended solve time... » read more

AI Won’t Kill Verification IP, But It Will Redefine It
By Ann Mutschler - 26 Mar, 2026 - Comments: 0

Key Takeaways AI will enhance, not replace, verification IP by automating test generation and debug. Verification IP’s core value will increasingly lie in trust, accountability, and system-level realism, especially as designs become more complex, multi-die, and security-sensitive. AI shifts verification bottlenecks from execution to specification quality, raising expectations for c... » read more

Scale AI: Engineering the Next Leap in LPDDR6 Low-Power Memory
By Keysight - 25 Mar, 2026 - Comments: 0

Scaling AI is often described as adding more GPUs and building bigger clusters, but real progress comes from system balance. As compute and throughput rise, pressure shifts to bandwidth, latency, power delivery, and thermal headroom. Memory becomes one of the earliest constraints because it sits on the critical path for feeding accelerators efficiently and consistently. In that context, JEDEC L... » read more

Beating The Heat In 3D Packages
By Laura Peters - 25 Mar, 2026 - Comments: 0

Key Takeaways: Thermal management is a central design constraint, requiring early, thorough planning. Accurate thermal simulation requires AI-driven adaptive meshing and real-world validation. Innovative STCO strategies can drastically reduce GPU peak temperature. As HPC and AI accelerators push power densities to 1kW and beyond, the heat generated by rapidly switching tran... » read more

Extraction Challenges of CFET and Backside Power Delivery
By Siemens EDA - 25 Mar, 2026 - Comments: 0

The integration of complementary field-effect transistors (CFETs) and buried power rails (BPRs) is central to advancing semiconductor scaling for nodes at 3nm and below. CFETs achieve unprecedented device density by vertically stacking n-type and p-type transistors, while BPRs embed the power network within the silicon substrate to boost efficiency and minimize area usage. These advances drive ... » read more

Building an AI Chip: Security, Software Development, and Lifecycle Management
By Synopsys - 25 Mar, 2026 - Comments: 0

The third white paper in our series, "Building an AI Chip" delves into the critical aspects of ensuring robust security and efficient software development for AI chips. As AI applications become increasingly integrated into everyday systems, the need for secure and reliable chip designs is paramount. This paper outlines essential strategies for safeguarding AI chip development, optimizing softw... » read more

Blog Review: Mar. 25
By Jesse Allen - 25 Mar, 2026 - Comments: 0

Synopsys' Jayraj Nair checks out how a model-based systems engineering workflow can help manage the complex multiphysics analysis needed to optimize heterogeneous systems. Siemens' Melville Bryant explains the difference between semiconductor traceability and tracking and why they're both essential, especially for complex multi-die devices. Cadence's Jamdagni Trivedi checks out VIP option... » read more

Chip Industry Technical Paper Roundup: Mar. 24
By Linda Christensen - 24 Mar, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations NL2GDS: LLM-aided interface for Open Source Chip Design 🔗 University of Bristol, Rutherford Appleton Laboratory An Integrated Failure and Threat Mode and Effect Analysis (FTMEA) Framework with Quantified Cross-Domain Correlation Factors for Automot... » read more

Research Bits: Mar. 24
By Jesse Allen - 24 Mar, 2026 - Comments: 0

Dual-modulated transistor Researchers from Daegu Gyeongbuk Institute of Science and Technology (DGIST) and University of Cambridge designed dual-modulated vertically stacked transistors in which two gates, positioned above and below in a sandwich-like structure, control the channel through different mechanisms. The lower electrode contains microscopic openings to allow electric signals to p... » read more

Auto Ethernet 10BASE-T1S Steps Up, With Tbps On The Horizon
By Liz Allan - 23 Mar, 2026 - Comments: 0

Key Takeaways: Automotive Ethernet, particularly 10BASE-T1S, is emerging as a replacement for CAN in vehicle networks, with higher speeds anticipated for future autonomous and connected cars. The transition to Ethernet in automotive domains is not universal; some OEMs may retain CAN or LIN in certain areas due to cost, and integrating various Ethernet standards can be technically feasib... » read more

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