Verifying Hardware CWEs in RTL Designs Generated by GenAI
By Technical Paper Link - 27 Mar, 2024 - Comments: 0

A new technical paper titled "All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification" was published by researchers at Infineon Technologies. Abstract "Modern hardware designs have grown increasingly efficient and complex. However, they are often susceptible to Common Weakness Enumerations (CWEs). This paper is focused on the formal verification of CWEs in a dataset... » read more

V2X Security Is Multi-faceted, And Not All There
By Ann Mutschler - 27 Mar, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss Vehicle-To-Everything (V2X) technology and potential security issues, with Shawn Carpenter, program director, 5G and space at Ansys; Lang Lin, principal product manager at Ansys; Daniel Dalpiaz, senior manager product marketing, Americas, green industrial power division at Infineon; David Fritz, vice president of virtual and hy... » read more

Everything You Need to Know About Wi-Fi 7
By Keysight - 27 Mar, 2024 - Comments: 0

The IEEE 802.11be standard introduces several new features for improving WLAN efficiency, capacity, and coverage. Features such as multi-link operation (MLO) and multiple resource units (multi-RUs) increase the number of configurations and test scenarios to validate a device thoroughly. In addition to physical-layer testing, test engineers must emulate signaling to verify interactions between a... » read more

Leveraging Automotive Chip Design Techniques For Space-Borne Applications
By Synopsys - 27 Mar, 2024 - Comments: 0

Space-borne electronics must operate in an unforgiving environment with harsh conditions and little opportunity to repair failing components. A combination of functionally safe design, RHBD, and robust IP is required. Fortunately, automotive applications share many of the same challenges, and techniques to address these challenges are well established and proven. This white paper surveys the ma... » read more

Sea Of Processors Use Case
By Movellus - 27 Mar, 2024 - Comments: 0

Core counts have been increasing steadily since IBM's debut of the Power 4 in 2001, eclipsing 100 CPU cores and over 1,000 for AI accelerators. While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always going to be symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialize... » read more

Cadence Cerebrus In SaaS And Imagination Technologies Case Study
By Cadence - 27 Mar, 2024 - Comments: 0

Artificial Intelligence (AI) has made noteworthy progress and is now ready and available for electronic design automation. The Cadence Cerebrus Intelligent Chip Explorer utilizes AI—specifically, reinforcement machine learning (ML) technology—combined with the industry-leading Cadence digital full flow to deliver better power, performance, and area (PPA) more quickly. However, this highl... » read more

Blog Review: Mar. 27
By Jesse Allen - 27 Mar, 2024 - Comments: 0

Cadence's Steve Brown suggests that multi-die technologies will be a key part of the path toward a faster, more efficient chip ecosystem that can support the compressed development cycles now emerging in the automotive industry. Synopsys' John Swanson, Madhumita Sanyal, and Priyank Shukla point to the role of simulation in ensuring seamless operation in the Ethernet ecosystem though rigorous... » read more

The Data Crisis Is Unfolding — Are We Ready?
By Alphawave Semi - 27 Mar, 2024 - Comments: 0

The rapid advancement of technology has led to an unprecedented amount of data being generated, captured, and consumed globally. However, this reliance on data comes at a considerable cost. The widespread sharing and processing of data is necessary to navigate our everyday lives. Still, any disruption to this process can have severe consequences, threatening our ability to function as a society... » read more

DRAM Cache for GPUs With SCM And High Bandwidth
By Technical Paper Link - 26 Mar, 2024 - Comments: 0

A new technical paper titled "Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory" was published by researchers at POSTECH and Songsil University. Abstract "We propose overcoming the memory capacity limitation of GPUs with high-capacity Storage-Class Memory (SCM) and DRAM cache. By significantly increasing the memory capacity with SCM, the GPU can capture a larger fraction o... » read more

Chip Industry Technical Paper Roundup: March 26
By Linda Christensen - 26 Mar, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=209 /] Find last week's technical paper additions here. » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy