LAB Flip Chip Reflow Process Robustness Prediction By Thermal Simulation

By Gabriel Chang - 16 Nov, 2023 - Comments: 0

By Gabriel Chang and Ricky Zang Nowadays, there are many interconnects in IC chips. One of the packaging goals is to connect an IC to the next level of subsystem circuitry (package substrates/print circuit boards). Mass reflow (MR) of solder joints is a widely adapted and stable process in the industry. The applications of MR include flip chip, ball mounting, surface mount technology (SMT), ... » read more

Increasing AI Energy Efficiency With Compute In Memory

By Katherine Derbyshire - 16 Nov, 2023 - Comments: 0

Skyrocketing AI compute workloads and fixed power budgets are forcing chip and system architects to take a much harder look at compute in memory (CIM), which until recently was considered little more than a science project. CIM solves two problems. First, it takes more energy to move data back and forth between memory and processor than to actually process it. And second, there is so much da... » read more

What Is TCAD And Why It Is Essential For The Semiconductor Industry

By Shela Aboud - 16 Nov, 2023 - Comments: 0

Modern technology computer-aided design (TCAD) technologies have been around now for years. Yet, many semiconductor engineers still run experiments directly on wafers to examine chip fabrication processes and device operation. While it can be challenging to become proficient in TCAD, conducting experiments on wafers isn’t exactly easy, nor is it quick or cost-effective to do. As with so ma... » read more

Center For Deep Learning In Electronics Manufacturing: Bringing Deep Learning To Production For Photomask Manufacturing

By Jan Willis - 16 Nov, 2023 - Comments: 0

The Center for Deep Learning in Electronics Manufacturing (CDLe) was formed as an alliance between D2S, Mycronic and NuFlare Technology in autumn 2018. Assignees from each alliance partner worked with deep learning (DL) experts under the leadership of Ajay Baranwal, director of CDLe. The CDLe’s mission was to 1) turn DL into a core competency inside each of the companies and 2) do DL projects... » read more

Analysis Of BEOL Metal Schemes By Process Modeling

By Daebin Yim - 16 Nov, 2023 - Comments: 0

The semiconductor industry has been diligently searching for alternative metal line materials to replace the conventional copper dual damascene scheme, because as interconnect dimensions shrink, the barrier accounts for an increasing fraction of the total line volume. The barrier layer's dimensions cannot be scaled down as quickly as the metal line width (figure 1). Popular barrier materials su... » read more

Maximizing Edge Intelligence Requires More Than Computing

By Toshikazu Nishida - 16 Nov, 2023 - Comments: 0

By Toshi Nishida, Avik W. Ghosh, Swaminathan Rajaraman, and Mircea Stan Commercial-off-the-shelf (COTS) components have enabled a commodity market for Wi-Fi-connected appliances, consumer products, infrastructure, manufacturing, vehicles, and wearables. However, the vast majority of connected systems today are deployed at the edge of the network, near the end user or end application, opening... » read more

Transforming Semiconductor Manufacturing: How AI And ML Boost Productivity And Beat The Skill Shortage

By David Park - 16 Nov, 2023 - Comments: 0

In the fast-paced world of semiconductor manufacturing, where innovation and efficiency are essential, there is a serious challenge – the persistent skilled labor shortage. As evident by billboards looking for workers along major highways, this shortage is not just a concern but a pressing reality. Semiconductor manufacturers in the United States face a multifaceted problem—tightened... » read more

Curvilinear Mask Patterning For Maximizing Lithography Entitlement

By Synopsys - 15 Nov, 2023 - Comments: 0

Curvilinear Mask Patterning is a cutting-edge lithography technique that promises to maximize lithography entitlement by addressing complex design challenges and critical yield limiters. However, its widespread deployment has been limited by significant computational challenges. This paper includes practical solutions to overcome the computational challenges associated with this technique, as w... » read more

Blog Review: November 15

By Jesse Allen - 15 Nov, 2023 - Comments: 0

Cadence's Neelabh Singh explores the process of lane initialization and link training in bringing up a high-speed link in USB4. Synopsys' Shela Aboud argues that TCAD should be an integral part of an EDA flow as it enhances design technology co-optimization with a way to experiment and determine what works and what doesn’t work at different process nodes using physics-based models. Siem... » read more

What Can Go Wrong In Heterogeneous Integration

By Ed Sperling - 15 Nov, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss heterogeneous integration with Dick Otte, president and CEO of Promex Industries; Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology; Shekhar Kapoor, senior director of product management at Synopsys; John Park, product management group director in Cadence's Custom IC & PCB Group; and Tony Mastroia... » read more

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