Multi-Channel Ultra Ethernet TSS Complete Layer


In the data center environment, the servers, storage and AI/HPC clusters need to move confidential data quickly and securely. Traditionally, RDMA is used as a transport protocol along with the network security based on MACsec and IPsec ESP protocols. To improve efficiency of using Ethernet in AI/HPC systems, the Ultra Ethernet Consortium introduced the new, IP-based transport protocol (UET), al... » read more

Blog Review: Mar. 4


Cadence's Subash Peddu digs into the challenge of balancing performance, power efficiency, SoC layout optimization, and futureproofing when defining SoCs and memory subsystems for tomorrow’s AI accelerators. Siemens' Nicolae Tusinschi suggests that formal verification isn't just about finding bugs, and the ability to achieve mathematical certainty can fundamentally change how hardware desi... » read more

New Challenges In Signoff


Multi-die assemblies coupled with leading-edge process nodes make signoff increasingly challenging and scary. There are more corner cases and more data to consider, but no slack in the delivery schedule. Marc Heyberger, product engineer group director at Cadence Design Systems, talks about full-chip timing, flat versus hierarchical timing analysis, the ongoing development of full 3D-ICs, and wh... » read more

Research Bits: Mar. 3


Computational electron microscopy Researchers from Cornell University, TSMC, and ASM used electron ptychography for atomic-scale defect inspection of transistors. The computational imaging method uses an extremely precise electron microscope pixel array detector (EMPAD) to collect detailed scattering patterns of electrons after they pass through transistors and compare how the patterns chan... » read more

Chip Industry Technical Paper Roundup: Mar. 3


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance 🔗 KAIST, Panmnesia, Peking University, Hanyang University, Pennsylvania State University Sputtering-driven formation of interstitial oxygen for intrinsic NIR detec... » read more

Follow The AI Leader


In the 1980s, a common expression was "nobody ever got fired for buying IBM." It was considered the safe option, long after new technologies had emerged. While it may not have been the most advanced option available, it remained the safe bet. It had an established ecosystem, and it was a known quantity. But who or what is the safe bet when it comes to AI? Who has the necessary data? Who has ... » read more

5 Systems-Level Attack Surfaces That Are Architectural Consequences of Edge-Local Deployment (Imperial College London)


Researchers from Imperial College London and Bytedance released “Systems-Level Attack Surface of Edge Agent Deployments on IoT”. Abstract “Edge deployment of LLM agents on IoT hardware introduces attack surfaces absent from cloud-hosted orchestration. We present an empirical security analysis of three architectures (cloud-hosted, edge-local swarm, and hybrid) using a multi-devic... » read more

Oxide-Semiconductors For Gain Cell Memory Applications (SNU, KAIST)


Researchers from Seoul National University and KAIST published “Oxide Semiconductor Gain Cell-Embedded Memory: Materials and Integration Strategies for Next Generation On-Chip Memory”. Abstract “The data processing demands of the digital era have exposed limitations in conventional memory architectures. Gain cell-embedded dynamic random-access memory based on oxide semiconductor... » read more

Extending Formal Verification to Sequential Circuits (U. of Bremen)


Researchers from University of Bremen have released “Linear Formal Verification of Sequential Circuits using Weighted-AIGs”. Abstract "Ensuring the functional correctness of a digital system is achievable through formal verification. Despite the increased complexity of modern systems, formal verification still needs to be done in a reasonable time. Hence, Polynomial Formal Verifica... » read more

Accelerate Your IP Selection With Smart Solido Library Profiler


This white paper discusses the IP selection process, its requirements, challenges, and proposed solutions. The process of choosing cell IP libraries for integrated circuit (IC) design is a slow and complicated process due to the inconsistencies and complexities of library files, particularly across sources, technology nodes, and variants. Manual methods to achieve IP selection not only consumes... » read more

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