Chip Industry Technical Paper Roundup: Feb. 24


New technical papers recently added to Semiconductor Engineering’s library: [table id=525 /] Find more semiconductor research papers here. » read more

Research Bits: Feb. 24


Growing patterned diamond Researchers from Rice University developed a bottom-up microwave plasma chemical vapor deposition method for growing patterned diamond surfaces that could help decrease operating temperatures in electronics by 23 degrees Celsius. The team used two techniques for controlling seed crystal placement. Photolithography was used for small, detailed patterns. To scale up ... » read more

Chiplets 2026: Where Are We Today?


Jim Handy of Objective Analysis and Jawad Nasrullah from Palo Alto Electron kicked off last week's Chiplet Summit with predictions about where the chiplet market is headed and why chiplets are needed to accelerate AI. Handy noted that in the 1990s, multi-chip modules (MCMs) led to mid-'90s multi-chip packages (MCPs), and then progressed to NAND flash stacking, stacked die, big chips (e.g., X... » read more

Ultrafast Laser Filamentation Dictates Energy Deposition in Narrow-Gap Semiconductors


A new technical paper, "Extreme optical nonlinearities unveiled by ultrafast laser filamentation in semiconductors," was published by researchers at Abbe Center of Photonics, Laboratoire Hubert Curien et al. Abstract "Sky-high optical nonlinearities make semiconductors ideal platforms for multifunctional photonic devices. The fabrication of such complex devices could greatly benefit from ... » read more

3D Atomic-Scale Metrology of Strain Relaxation And Roughness in GAAFETs Via Electron Ptychography (Cornell, ASM, TSMC)


A new technical paper, "3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography," was published by researchers at Cornell University, ASM and TSMC. Abstract "Next-generation semiconductor devices are adopting three-dimensional (3D) architectures with feature sizes in the few-nanometer regime, creating a need for atomic-scale me... » read more

ReRAM-based Neo-Hebbian Synapses For Training Neuromorphic HW (IIT Madras, UCSB)


A new technical paper, "NeoHebbian synapses to accelerate online training of neuromorphic hardware," was published by researchers at IIT Madras and UC Santa Barbara. Abstract "Neuromorphic systems that employ advanced synaptic learning rules, such as the three-factor learning rule, require synaptic devices of increased complexity. Herein, a novel neoHebbian artificial synapse utilizing ReRA... » read more

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers


Key Takeaways Backside power delivery reduces routing congestion at the most advanced nodes and offers significant performance improvement options. But it also adds a bunch of new challenges involving via alignment and interconnects. Still, leading-edge foundries are making progress, and all of them plan to offer BPDNs at 2nm and below. Backside power delivery networks deliv... » read more

New Performance Requirements For Audio


Demand for higher performance in audio is rising as human-machine interactions increase on the edge. That means more processing elements, and more challenges in keeping data consistent across those processors. Prakash Madhvapathy, director of product marketing and product management at Cadence, talks about the advantages of coherent designs, how that impacts security, and how DSPs are evolving ... » read more

Survey of GenAI Across the Full Computing Stack, From SW To Silicon (Harvard)


Harvard University researchers published "GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon." Abstract "Generative AI is reshaping how computing systems are designed, optimized, and built, yet research remains fragmented across software, architecture, and chip design communities. This paper takes a cross-stack perspective, examining how generative models... » read more

Accelerator Architecture: Fusion-Aware Mapper (MIT)


Researchers from MIT published "Fast and Fusiest: An Optimal Fusion-Aware Mapper for Accelerator Modeling and Evaluation." Abstract "The latency and energy of tensor algebra accelerators depend on how data movement and operations are scheduled (i.e., mapped) onto accelerators, so determining the potential of an accelerator architecture requires both a performance model and a mapper to sea... » read more

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