Carrier mapping in sub‑2nm; CNN-to-edge HLS; sandpaper for atomic-precision surface finishing; LLM chip design education; nanolaser with extreme dielectric confinement; germanium-tin alloy semiconductors; low-voltage nanoscale MoS2 memristors; scaling routers with in-package optics and HBM4; RISC-V security.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Carrier Mapping in Sub-2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy | imec and KU Leuven |
| An Automated CNN-to-Edge MLIR HLS framework | TU Dresden |
| Carbon nanotube sandpaper for atomic-precision surface finishing | KAIST |
| From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs | RPTU University of Kaiserslautern-Landau |
| A nanolaser with extreme dielectric confinement | DTU |
| High Pressure and Compositionally Directed Route to a Hexagonal GeSn Alloy Class | University of Edinburgh et al. |
| Integration of Low-Voltage Nanoscale MoS2 Memristors on CMOS Microchips | RWTH Aachen and Forschungszentrum Jülich |
| Scaling Routers with In-Package Optics and HBMs | Technion, UC Berkeley and UC San Diego |
| Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs | CISPA |
Find more semiconductor research papers here.
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