Blog Review: May 10


Synopsys' Alessandra Nardi and Uyen Tran explain how to meet quality, reliability, functional safety, and security requirements of automotive chips through thorough test programs, path-margin monitoring, and design failure mode and effect analysis (DFMEA). Cadence's Veena Parthan explores how computational fluid dynamics can help predict and model the generation, propagation, and mitigation ... » read more

Research Bits: May 10


Growing 2D TMDs on chips Researchers from Massachusetts Institute of Technology (MIT), Oak Ridge National Laboratory, and Ericsson Research found a way to “grow” layers of 2D transition metal dichalcogenide (TMD) materials directly on top of a fully fabricated silicon chip, a technique they say could enable denser integrations. The researchers focused on molybdenum disulfide, which is f... » read more

Achieving Your Low Power Goals With Synopsys Ultra Low Leakage IO


The demand for low power design has intensified with shrinking geometries. At the same time, innovation in battery operated, handheld devices has increased the design complexity by adding more and more functionality. The focus is on power-optimized designs while maintaining low cost and reduced risk. Designers face these complex and contradictory challenges: developing products with the lowest ... » read more

Designing Crash-Proof Autonomous Vehicles


Autonomous vehicles keep crashing into things, even though ADAS technology promises to make driving safer because machines can think and react faster than human drivers. Humans rely on seeing and hearing to assess driving conditions. When drivers detect objects in front of the vehicle, the automatic reaction is to slam on the brakes or swerve to avoid them. Quite often drivers cannot react q... » read more

Performance Of Analog In-Memory Computing On Imaging Problems


A technical paper titled "Accelerating AI Using Next-Generation Hardware: Possibilities and Challenges With Analog In-Memory Computing" was published by researchers at Lund University and Ericsson Research. Abstract "Future generations of computing systems need to continue increasing processing speed and energy efficiency in order to meet the growing workload requirements under stringent en... » read more

Circuit Layout-Level Hardware Trojan Detection


A new technical paper titled "A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware Trojans" was published by researchers at The University of Texas at Dallas and Qualcomm. Abstract "Distributed integrated circuit (IC) supply chain has resulted in a myriad of security vulnerabilities including that of hardware Trojan (HT). An HT can perform malicious modifications on an I... » read more

28nm-HKMG-Based FeFET Devices For Synaptic Applications


A technical paper titled "28 nm high-k-metal gate ferroelectric field effect transistors based synapses- A comprehensive overview" was published by researchers at Fraunhofer-Institut für Photonische Mikrosysteme IPMS, Indian Institute of Technology Madras, and GlobalFoundries. Abstract This invited article we present a comprehensive overview of 28 nm high-k-metal gate-based ferroelectric f... » read more

Reconfigurability and NTC-based Signal Modulation Within a Single Ferroelectric TFET


A new technical paper titled "Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor" was published by researchers at Lund University in Sweden. Abstract: "Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we ... » read more

Smelling The Metaverse Via Wearable Wireless Interfaces


A new technical paper titled "Soft, miniaturized, wireless olfactory interface for virtual reality" was published by researchers at  City University of Hong Kong, Hong Kong Science Park, Beihang University, and others. Abstract "Recent advances in virtual reality (VR) technologies accelerate the creation of a flawless 3D virtual world to provide frontier social platform for human. Equall... » read more

Pinpointing Timing Delays Can Improve Chip Reliability


Growing pressure to improve IC reliability in safety- and mission-critical applications is fueling demand for custom automated test pattern generation (ATPG) to detect small timing delays, and for chip telemetry circuits that can assess timing margin over a chip's lifetime. Knowing the timing margin in signal paths has become an essential component in that reliability. Timing relationships a... » read more

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