MIT & UC Berkeley: “Exo” Programming Language Writes High Performance Code For HW Accelerators
By Technical Paper Link - 11 Jul, 2022 - Comments: 0

New research paper titled "Exocompilation for productive programming of hardware accelerators," from researchers at MIT and UC Berkeley. From their abstract: "To better support development of high-performance libraries for specialized hardware, we propose a new programming language, Exo, based on the principle of exocompilation: externalizing target-specific code generation support and op... » read more

Technical Paper Round-up: July 11
By Linda Christensen - 11 Jul, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=38 /]   Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a ... » read more

Implementing Memory Encryption To Protect Data In Use
By Rocky Zhang - 11 Jul, 2022 - Comments: 0

In my blog “The Methods of Memory Encryption to Protect Data in Use,” I discussed how the XTS/XEX mode of encryption was the appropriate choice for protecting data stored in and accessed from memory, also known as, protecting data in use. As a quick recap, XTS/XEX uses two keys, one key for block encryption, and another key to process a “tweak.” The tweak ensures every block of memory i... » read more

Research Bits: July 11
By Jesse Allen - 11 Jul, 2022 - Comments: 0

Modeling ALE Scientists at U.S. Department of Energy’s (DOE) Princeton Plasma Physics Laboratory (PPPL), in coordination with Lam Research, modeled atomic layer etching (ALE) for semiconductor fabrication. “This would be one little piece in the whole process,” said David Graves, associate laboratory director for low-temperature plasma surface interactions at PPPL and a professor in th... » read more

Electromagnetic Simulation And 3D-IC Interposers
By Matt Commens - 11 Jul, 2022 - Comments: 0

By Matt Commens, Juliano Mologni, and Pete Gasperini Today’s 3D integrated circuit (3D-IC) technology is the culmination of 40 years of research in universities and laboratories scattered across the globe. Beginning with dynamic random-access memory (DRAM) deployments that appeared on the market a decade ago, 3D-IC has since expanded its reach. It is now decisively beginning to achieve the... » read more

FEOL Nanosheet Process Flow & Challenges Requiring Metrology Solutions (IBM Watson)
By Technical Paper Link - 08 Jul, 2022 - Comments: 0

New technical paper titled "Review of nanosheet metrology opportunities for technology readiness," from researchers at IBM Thomas J. Watson Research Ctr. (United States). Abstract (partial): "More than previous technologies, then, nanosheet technology may be when some offline techniques transition from the lab to the fab, as certain critical measurements need to be monitored in real time. T... » read more

Attenuated Phase Shift Masks (attPSM) For EUV (Fraunhofer IISB)
By Technical Paper Link - 08 Jul, 2022 - Comments: 0

New research paper titled "Attenuated phase shift masks: a wild card resolution enhancement for extreme ultraviolet lithography?," from researchers at Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB (Germany). Aim: "We review published research on attenuated phase shift masks (attPSM) for EUV with special emphasis on modeling and fundamental understanding of the ... » read more

ISA Extension For Low-Precision NN Training On RISC-V Cores
By Technical Paper Link - 08 Jul, 2022 - Comments: 0

New technical paper titled "MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores" from researchers at IIS, ETH Zurich; DEI, University of Bologna; and Axelera AI. Abstract "Low-precision formats have recently driven major breakthroughs in neural network (NN) training and inference by reducing the memory footprint of the N... » read more

Delay-based PUF for Chiplets to Verify System Integrity
By Technical Paper Link - 08 Jul, 2022 - Comments: 0

New technical paper titled "Know Time to Die – Integrity Checking for Zero Trust Chiplet-based Systems Using Between-Die Delay PUFs" by researchers at University of Massachusetts, Amherst MA, Abstract (partial): "In this paper we propose a delay-based PUF for chiplets to verify system integrity. Our technique allows a single chiplet to initiate a protocol with its neighbors to measure un... » read more

Week In Review, Manufacturing, Test
By SE Staff - 08 Jul, 2022 - Comments: 0

The U.S. is attempting to restrict sales of ASML’s deep ultra-violet (DUV) litho systems to China, according to a report from Bloomberg. The U.S. has been working to limit China's access to advanced technology for some time, and it has already limited sales of extreme ultra-violet (EUV), which is used to develop chips at the most advanced process nodes. DUV, in contrast, is used for older-nod... » read more

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