2.5D And 3D-IC Latch-Up Prevention
By Siemens EDA - 11 Aug, 2021 - Comments: 0

2.5D/3D ICs have evolved into an innovative solution for many design and integration situations, but they present unique verification obstacles that challenge electronic design automation (EDA) tools originally designed for 2D ICs. Automated solutions are needed not only to reduce verification cycles but also to improve the quality and reliability of package designs. Automated verification o... » read more

Has Computational Storage Finally Arrived?
By Andy Patrizio - 11 Aug, 2021 - Comments: 2

The idea behind computational storage is not new. It’s just that like so many concepts, the idea has been well ahead of the technology. In a nutshell, computational storage brings processing power to the storage level. It eliminates the need to load data from the storage system into memory for processing. Moving data between storage and compute resources is inefficient and computational sy... » read more

Radar Wave Propagation Through Materials
By Infineon - 11 Aug, 2021 - Comments: 0

This white paper focuses on electromagnetic (EM) wave propagation through materials. For radar systems, this is of interest when radar must pass through walls, or when designing radomes (cover casings for the radar system). In the process of designing a radome, you should always perform full EM simulation. However, the content of this white paper will help you to first estimate whether a radome... » read more

Post-Quantum Cryptography
By Arm - 11 Aug, 2021 - Comments: 0

Quantum computing is increasingly seen as a threat to communications security: rapid progress towards realizing practical quantum computers has drawn attention to the long understood potential of such machines to break fundamentals of contemporary cryptographic infrastructure. While this potential is so far firmly theoretical, the cryptography community is preparing for this possibility by deve... » read more

10X Higher Productivity With VCS Dynamic Test Loading
By Synopsys - 11 Aug, 2021 - Comments: 0

The verification of a system-on-chip (SoC) is becoming increasingly complex, due to the multitude of functionality being implemented on a single chip. Different verification techniques are required at each level (IP, block, SoC and system) for faster verification closure. A successful verification strategy requires reuse of functional tests, faster test development and faster debug to improve t... » read more

Blog Review: Aug. 11
By Jesse Allen - 11 Aug, 2021 - Comments: 0

Arm's Rahul Mathur finds that traditional interconnects have become a bottleneck for improving IC performance and suggests buried interconnects as a way to lower signal routing delay. Cadence's Paul McLellan checks out forksheet FETs, a new transistor type that could allow scaling past 3nm, and the interconnect advances that will need to accompany it. A Synopsys writer explains the new LP... » read more

Designing Chips For Test Data
By Ed Sperling - 10 Aug, 2021 - Comments: 0

Collecting data to determine the health of a chip throughout its lifecycle is becoming necessary as chips are used in more critical applications, but being able to access that data isn't always so simple. It requires moving signals through a complex, sometimes unpredictable, and often hostile environment, which is a daunting challenge under the best of conditions. There is a growing sense of... » read more

Harness System-Level Data To Optimize Many-Core AI And ML Chips
By Siemens EDA - 10 Aug, 2021 - Comments: 0

The novel multicore architectures of SoCs for machine learning (ML) and artificial intelligence (AI) applications are expected to deliver huge improvements in power efficiency. However, chip development teams and the customers for their devices face the growing complexity of hardware-software co-optimization, validation, and debug. In short, these SoCs are increasingly difficult to validate and... » read more

Power-Aware Test: Addressing Power Challenges In DFT And Test
By Rahul Singhal - 10 Aug, 2021 - Comments: 0

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design sizes increase, the total power consumption of the chip also increases. While process node scaling reduces a transistor’s size and its operating-voltage, power scaling has not kept up with the si... » read more

Reducing Rework In CMP: An Enhanced Machine Learning-Based Hybrid Metrology Approach
By Vamsi Velidandla - 10 Aug, 2021 - Comments: 0

By Vamsi Velidandla, John Hauck, Zhuo Chen, Joshua Frederick, and Zhihui Jiao The semiconductor industry is constantly marching toward thinner films and complex geometries with smaller dimensions, as well as newer materials. The number of chemical mechanical planarization (CMP) steps has increased and, with it, a greater need for within-wafer uniformity and wafer-to-wafer control of the thin... » read more

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