Shift Left Verification With Comprehensive Lint Signoff
By Synopsys - 08 Jul, 2020 - Comments: 0

With soaring complexity and continuously increasing chip sizes, achieving efficient and predictable design closure has become a prominent challenge among designers today. Demand for a faster time to market is forcing designers to find ways to shorten design cycles with accurate, efficient, one-time RTL to silicon. To meet these requirements designers are looking to implement early ”shift left... » read more

Multiphysics Reliability Signoff For Next-Generation Automotive Electronics Systems
By Ansys - 08 Jul, 2020 - Comments: 0

Automotive electronics systems depend on an ever-increasing number of electronic sensors and processing elements, which allow for 360-degree surveillance and object identification/classification. Designing and verifying these systems is, however, as complex as the systems themselves. This white paper examines how automotive chip designers can achieve the stringent safety and reliability requ... » read more

Startup Funding: June 2020
By Jesse Allen - 08 Jul, 2020 - Comments: 0

Two Chinese startups drew big investment as the country aims to become more semiconductor independent as trade restrictions continue. One company deals in wafers, packaging, and IC design, while the other is focused on AI chips. Quantum computing startups didn't see large investments this month, as most are still very young companies, but the number of them grew with a new university spin-out e... » read more

Next Challenge: Known Good Systems
By Ed Sperling - 07 Jul, 2020 - Comments: 0

The leading edge of design is heading toward multi-die/multi-chiplet architectures, and an increasing number of mainstream designs likely will follow as processing moves closer to the edge. This doesn't mean every chipmaker will be designing leading-edge chips, of course. But more devices will have at least some leading-edge logic or will be connected over some advanced interconnect scheme t... » read more

Probing From Home
By Anthony Lord - 07 Jul, 2020 - Comments: 0

The current stay-at-home, work-from-home situation challenges the semiconductor industry in a way we have never seen before. Social distancing and remote work put operational procedures in place that can be difficult. In a previous post, we shared information on our virtual demos designed to help keep your semiconductor measurements running no matter where you are physically located. In this ... » read more

Advanced Packaging Makes Testing More Complex
By Bryon Moyer - 07 Jul, 2020 - Comments: 1

The limits of monolithic integration, together with advances in chip interconnect and packaging technologies, have spurred the growth of heterogeneous advanced packaging where multiple dies are co-packaged using 2.5D and 3D approaches. But this also raises complex test challenges, which are driving new standards and approaches to advanced-package testing. While many of the showstopper issues... » read more

Monitoring IC Abnormalities Before Failures
By Anne Meixner - 07 Jul, 2020 - Comments: 0

The rising complexities of semiconductor processes and design are driving an increasing use of on-chip monitors to support data analytics from an IC’s birth through its end of life — no matter how long that projected lifespan. Engineers have long used on-chip circuitry to assist with manufacturing test, silicon debug and failure analysis. Providing visibility and controllability of inter... » read more

Adopting Yield Analysis Tools
By Marie Ryan - 07 Jul, 2020 - Comments: 0

DisplayLink is a fast growing medium-sized semiconductor fabless company from Cambridge UK. We began working with them a few years ago. We caught up with Shane Zhang, Head of Product Engineering to find out why he works with yieldHUB, the problems we solve and the features he likes most. Tell us about DisplayLink. Our operations team is based in Cambridge, UK. We work with teams, suppli... » read more

Design And Measurement Requirements For Short Flow Test Arrays To Characterize Emerging Memories
By PDF Solutions - 07 Jul, 2020 - Comments: 0

Emerging non-volatile memories are becoming increasingly attractive for embedded and storage-class applications. Among the development challenges of Back-End integrated memory cells are long learning cycle and high wafer cost. We propose a short-flow based characterization of Memory Arrays using a Cross Point Array approach. A detail analysis of design requirements and testability confirms feas... » read more

Test Setup Optimization And Automation For Accurate Silicon Photonics Wafer Acceptance Production Tests
By FormFactor - 07 Jul, 2020 - Comments: 0

Implementing energy-efficient optical transceiver modules with silicon photonics (SiPh) and 3DIC technologies will help alleviate the increasing energy consumption for hyperscale data centers. To facilitate effective 3DIC heterogenous integration of these photonics integrated circuits for optical transceivers, high precision, repeatable and reliable SiPh wafer acceptance tests are essential and... » read more

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