category: Blogs – LPHP

category: Auto, Security & Edge AI

The Power Of eDRAM
By Barry Pangrle - 16 Jun, 2014 - Comments: 1

In last month’s article we looked at different aspects of technology nodes and the multiple techniques that are used to keep scaling on its path of increasing density. From an energy standpoint, it’s expensive to move data around and with the high bandwidth that’s needed to keep processors “fed,” engineers are looking at ways to keep data closer to the processing logic and minimize th... » read more

Does EDA Consider RTL Power Optimization As Job Done?
By Mark Baker - 13 Jun, 2014 - Comments: 0

The “Power Buzz” leading into this year’s Design Automation Conference was around System Level Power Architecture and Optimization—some would say the natural progression of EDA towards the next big customer design challenge. This does beg the question of whether EDA considers RTL Power Optimization a mature solution. All products or solutions progress through various stages of maturity,... » read more

Processor IP Enabling The Wearable Trend
By Ellie Stone - 12 Jun, 2014 - Comments: 0

Wearable technology is one of the fastest growing market segments. It is expected to be the next big thing in the field of computing and could, over the next decade, become as large as the mobile market is today. Its growth will depend on innovative devices providing a better user experience to their non-wearable alternatives, as well as broad availability of these products backed by a supporti... » read more

FinFET-Based Designs: Package Model Considerations
By Aveek Sarkar - 12 Jun, 2014 - Comments: 0

The use of FinFET devices in next-generation high-performance, low-power designs is a fundamental shift that is happening in the semiconductor industry. These devices through their smaller sizes, tighter Vth control and higher drive strengths enable higher performance and increased integration while reducing overall energy consumption. But along with their advantages these devices introduce and... » read more

Power IS Top Priority, Isn’t It?
By Ann Mutschler - 12 Jun, 2014 - Comments: 0

While I don’t mean to start a battle – or maybe I do! – I heard something last week during DAC that gave me pause. The person I was speaking with – who told me they ‘got in a little bit of trouble’ for saying this – reminded me of an interesting subject we had talked about previously, namely, that they did not believe power is the number one concern of engineering teams today. Ye... » read more

As Nodes Advance, So Must Power Analysis
By Mentor, a Siemens Business - 12 Jun, 2014 - Comments: 0

By Chetandeep Singh and Ravi Tangirala Smaller geometry nodes offer cost and performance advantages that encourage their adoption. Yet they present a new set of challenges for IC manufacturers: Though transistors are smaller, they leak more current. This is an important issue as the demand for high-performance, battery-operated, system-on-chips (SoC) in communication and computing shifts th... » read more

Rethinking Low Power Verification: LP + CDC Verification
By David Hsu - 12 Jun, 2014 - Comments: 1

In my last posting, we discussed some of the barriers that companies face in seeking to meet their low power verification objectives, and how the complete and integrated technologies in Synopsys’ new Verification Compiler product can help. This time, I’d like to introduce a relevant example of how unified technology solutions can help address complex design interactions in low power verific... » read more

Computer Vision’s Enormous Challenges Ahead
By Brian Fuller - 12 Jun, 2014 - Comments: 0

SAN FRANCISCO — There is a constant, humming tension between what Moore's Law delivers and what consumers expect from electronics systems design. We're on the verge of seeing this in the coming decade in computer vision, an application that has enormous potential to transform society. In the meantime, enormous challenges and decisions lie ahead on the road to transformation. Embedded Vi... » read more

A Node By Any Other Name
By Barry Pangrle - 12 May, 2014 - Comments: 3

Have you ever wondered what gives a particular CMOS technology node its name? When we talk about 20nm, 16nm or 14nm, what exactly does that number in front of the “nm” mean anyway? Is it the first layer metal half-pitch or the gate length (and while we’re at it, is that the printed gate length, the physical gate length, or the effective gate length)? The half-pitch refers to half the m... » read more

Memory Matters For Mid-Range Mobile Devices
By Ajay Jain - 09 May, 2014 - Comments: 2

In recent months, we’ve seen signs of saturation in the high-end mobile device market where smartphones and tablets retail for more than $300. The largest growth in the mobile device markets are in Asia, with China in particular showing an annual growth rate of more than 50% in the mid-range ($100-$299) market while low-end products retail for less than $50! Features like storage capacity,... » read more

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