Power Makes IP Integration More Fun


Remember the good old days at 130nm when it was easy to combine IP blocks on an SoC? All kidding aside, because obviously IP integration has always had its challenges, designers are experiencing new pain as process, voltage and temperature wreak havoc in bringing everything together and making sure it operates correctly, meeting all power requirements. As I discovered, whether IP comes from ... » read more

The ‘Hospital Pass’ Of Chip Design


By Ron Craig My wife is very understanding. Once every four years I become somehow distracted for 90 minute periods over the course of about a month, unresponsive to the most basic requests and occasionally straining to explain the minutiae of the offside trap, the beauty of the ‘nutmeg,’ the tactics of the three game group stage and why the flag didn’t go up because the left back on the... » read more

The Power Of The Customer Experience


By Barry Pangrle Consumers of electronics don’t buy chips, they buy products or gadgets. Sure the geeks among us may know about “the chip” in a PC, typically in reference to the CPU or maybe even the GPU. But there are many chips in the product and you’d have to be an über-geek to know all of them. How many customers actually know the primary SoC in their smart phone? The point is ... » read more

Knowing When To Panic


By Bhanu Kapoor Sometimes we hear that the number of power domains in SoCs have increased significantly and that makes power management verification difficult. True, the numbers have gone up from say 2 or 3 to between 7 and 10, but these are not large numbers by any means and you can write tests to ensure that each of these power domains are covered for power related tests. Power-related tests... » read more

Timing Closure And Denial


By Ron Craig I live in a reasonably remote area—defined as more than 10 miles from the nearest Starbucks. Given that I spend a fair amount of time driving, I’m conscious of things like safety and mileage. One thing that has a big impact on both is the health of my tires, and after having a recent replacement set installed I noticed that my ‘local’ tire shop offered things like regula... » read more

Giant Steps—Backward


With DAC headlining next week, power is sure to take center stage given its prominence as a key pain point for design engineers that are always on the lookout for a new technique to ease their power management burdens. In many low-power designs, asynchronous technology may be just the thing. One of the biggest disadvantages of the clockless CPU is that most design tools assume a clocked CPU ... » read more

Why So Formal?


By Bhanu Kapoor Let’s take a look at the types of power management verification issues that are most suited for formal verification and how formal techniques complement dynamic simulation-based verification in some of the challenging tasks associated with validating SoC power management architectures. There are three main categories of formal tools in use today: Equivalence Checkers, Asse... » read more

It’s The Architecture


Power optimization is a system issue. How many times have you experienced your cell phone provider sending your phone an update and the battery lifetime then improving? The hardware team built in the hooks but there just wasn't enough time to get the software together and tested before the product needed to ship, so the improved functionality shipped later. Well, that's at least one advanta... » read more

Optimizing Physical IP For Applications And Processors


What will the next challenges be for chip designers as the industry moves toward 28nm high-k metal gate manufacturing technology? One thing is for sure, power management may get even more painful without new innovations to handle the characteristics of 28nm. Optimization is definitely the approach that keeps creeping up as I talk with folks in the industry with ARM specifically mentioning ap... » read more

Money And Power


By Barry Pangrle Companies developing products work within the realms of cost, features and quality. As the old saying goes, “choose two.” For chip design teams, the budget for the production cost of the chip is usually a constraint that is handed to them. Often that budget is not just the cost of the silicon but the cost for a finished part that is tested and packaged and ready to ... » read more

← Older posts Newer posts →