Power Reduction In A Constrained World


Back when 40-28nm were new, leakage power for wireless designs dominated the optimization technology focus. This led to multiple VT optimization and power intent management for digital designs to minimize or shut off leakage. As wireless devices moved to FinFET nodes, dynamic power became dominant. As a result, optimization technology focus shifted to build up dynamic techniques to complement y... » read more

High-Performance Memory At Low Cost Per Bit


Hardware developers of deep learning neural networks (DNN) have a universal complaint – they need more and more memory capacity with high performance, low cost and low power. As artificial intelligence (AI) techniques gain wider adoption, their complexity and training requirements also increase. Large and complex DNN models do not fit on the small on-chip SRAM caches near the processor. This ... » read more

Getting Ahead With Early Power Analysis


Today’s mobile applications need to cater to a broad set of applications. They can be communications-heavy (Bluetooth and GPS), graphics-intensive (streaming 4K videos), or compute-intensive workloads (AR/VR gaming). At the heart of this processing lies the all-powerful mobile processor, which includes a multi-core CPU, GPU, memory and other IP and subsystems for performing a variety of ta... » read more

Impact Of IP On AI SoCs


The combination of mathematics and processing capability has set in motion a new generation of technology advancements with an entire new world of possibilities related to Artificial Intelligence. AI mimics human behavior using deep learning algorithms. Neural networks are what we define as deep learning, which is a subset of machine learning, which is yet a subset of AI, as shown in Figure 1. ... » read more

Minimizing The Risk Of Electromagnetic Crosstalk Failures


Leading semiconductor markets, such automotive, machine learning, large scale computing and networking, are driving the need for high density chips that integrate high performance digital cores with sensitive analog/RF IP, while operating at the lowest power and fastest bandwidth possible. These trends are increasing the sensitivity to electromagnetic (EM) coupling, and requiring designers to w... » read more

Predictive Maintenance In Tomorrow’s Industries


By Olaf Enge-Rosenblatt and Steven Brandt Tomorrow’s production plants must be efficient and adaptive, which is the key to survival in modern, highly competitive markets brought about by digitalization and automation. Future-oriented companies are increasingly focusing on a tight combination of automation and computer technology as promised by the Industry 4.0 paradigm. More and more globa... » read more

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation


I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification Methodology (UVM) is a standard library of SystemVerilog classes that supports a modular, reusable testbench architecture for constrained-random functional verification. Meanwhile, Mentor’... » read more

Pace Quickens As Machine Learning Moves To The Edge


Artificial intelligence applications are rapidly changing the way society engages with technology. It wasn’t too long ago that your smart phone couldn’t recognize your face or your thumbprint. It also wasn’t too long ago that Alexa wasn’t helping you navigate your day so easily. And not too long ago, odds are, you weren’t developing an application or device that had AI/ML as its ce... » read more

Taking Inductance And Electromagnetic Effects More Seriously


By Magdy Abadir and Yehea Ismail With increasing frequencies, tighter margins, denser integrated circuits, new devices and materials, the necessity of full EM analysis including magnetic/inductive effects is becoming a fundamental question for the industry. Where and when should full EM verification be included? Can some of major chip failures during development be attributed to ignoring ... » read more

Power-Aware Static Checks: Static Checker Results And Debugging Techniques


In Part 1 of this three article series on power aware (PA) verification, we examined the foundations and verification features of PA static checks. In Part 2, we discussed the features of the static verification library and described best static verification practices. Part 3 concludes this series with details of static PA verification tool procedures using a real example to analyze PA-Stati... » read more

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