category: Low Power-High Performance

category: Auto, Security & Edge AI

Research Bits: Feb. 9
By Jesse Allen - 09 Feb, 2026 - Comments: 0

Computing with heat Researchers from the Massachusetts Institute of Technology (MIT) designed silicon structures that can perform calculations in an electronic device using excess heat instead of electricity. The device was created using a software system that automatically designs a material that can conduct heat in a specific manner. The inverse design technique allowed the researchers to... » read more

Changes In Chip Architectures At The Edge
By Ed Sperling - 04 Feb, 2026 - Comments: 0

Edge computing is all about low latency, within a tight power budget, and with sufficient performance. This is very different from an AI data center, where the real focus is on data throughput between processor and memory. Achieving those goals requires a focus on what different processing elements bring to the table. Nigel Drego, co-founder and CTO of Quadric, talks about how these different c... » read more

Research Bits: Feb. 3
By Jesse Allen - 03 Feb, 2026 - Comments: 0

Artificial synapse Researchers from Ulsan National Institute of Science and Technology (UNIST) designed a biodegradable, energy efficient artificial synapse that uses a layered structure made from naturally-derived polymers that break down naturally within 16 days in soil. "The device is built like a tiny sandwich, with ion-active layers separated by an ion-binding layer made from cellulose... » read more

Chip Industry Technical Paper Roundup: Feb. 3
By Linda Christensen - 03 Feb, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=519 /] Find more semiconductor research papers here. » read more

Research Bits: Jan. 27
By Jesse Allen - 27 Jan, 2026 - Comments: 0

Analog in-memory compute Researchers from Politecnico di Milano, Peking University, and Hewlett Packard Labs developed a Closed-Loop In-Memory Computing (CL-IMC) chip to reduce data movement between memory and processor. The fully integrated analog accelerator uses two 64×64 arrays of programmable SRAM cells along with integrated components including operational amplifiers and analog-to-di... » read more

Balancing Training, Quantization, And Hardware Integration In NPUs
By Ann Mutschler - 26 Jan, 2026 - Comments: 0

Experts At The Table: AI/ML is driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down to discuss this with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Qu... » read more

Addressing Critical Tradeoffs In NPU Design
By Ann Mutschler - 21 Jan, 2026 - Comments: 1

Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven W... » read more

Research Bits: Jan. 20
By Jesse Allen - 20 Jan, 2026 - Comments: 0

ALD for Ru wiring Researchers from Ulsan National Institute of Science and Technology (UNIST), Hongik University, and Tanaka Precious Metal Technologies developed an atomic layer deposition (ALD) process for creating chip interconnects using a ruthenium (Ru) precursor with a thermal stability up to 400 °C. The high-temperature ALD process can produce dense, high-quality Ru films without deg... » read more

Engineering After Orthogonalization: Why Verification Has Become A Lifecycle Discipline
By Harry Foster - 15 Jan, 2026 - Comments: 0

Over the past several decades studying verification practices across the semiconductor industry, I’ve watched assumptions that once held up remarkably well begin to strain under the weight of modern system complexity. This is not a loss of engineering rigor. It is the result of systems that no longer conform to the boundaries earlier design models depended on. For much of the industry’s ... » read more

The Design Challenges Of Clock Integrity And Clock Jitter
By Manoz Palaparthi - 15 Jan, 2026 - Comments: 0

Signal integrity is one of the many challenges faced by chip designers. Deep submicron technologies are unfriendly hosts for the nice, clean signals desired. The culprits that compromise signal integrity and introduce jitter include thermal effects, manufacturing flaws, signal crosstalk, IR (voltage) drop, signal loss over long runs, reflections, electromagnetic interference (EMI), ground bounc... » read more

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