3 Technologies That Will Challenge Test


As chips are deployed in more complex systems and with new technologies, it's not clear exactly what chipmakers and systems vendors will be testing. The standard tests for voltage, temperature and electrical throughput still will be needed, of course. But that won't be sufficient to ensure that sensor fusion, machine learning, or millimeter wave 5/6G will be functioning properly. Each of tho... » read more

Reliability Costs Becoming Harder To Track


Ensuring reliability in chips is becoming more complex and significantly more expensive, shifting left into the design cycle and right into the field. But those costs also are becoming more difficult to define and track, varying greatly from one design to the next based upon process node, package technology, market segment, and which fab or OSAT is used. As the number of options increases fo... » read more

Is There a Practical Test For Rowhammer Vulnerability?


Rowhammer is proving to be a difficult DRAM issue to fix. While efforts continue to mitigate or eliminate the effect, no solid solution has yet made it to volume production. In addition, more aggressive process nodes are expected to exacerbate the problem. In the absence of a fix, then, testing may be one way to give DRAM manufacturers and users some way to segregate devices that are more su... » read more

Digging Much Deeper With Unit Retest


Keeping test costs flat in the face of product complexity continues to challenge both product and test engineers. Increased data collection at package-level test and the ability to respond to it in a never-before level of detail has prompted device makers and assembly and test houses to tighten up their retest processes. Test metrology, socket contamination, and mechanical alignment have alw... » read more

Expanded Material Metrology For Refined Etch Selectivities


Trends in advanced device fabrication require combined lithography-etching multi-patterning sequences and self-aligned multi-patterning to form devices’ finest features at subwavelength dimensions. As EUV lithography (13.5 nm) progresses to larger numerical apertures and new thin resists, new multipatterning sequences must be developed with mutually compatible resists and proximal layers t... » read more

Signal Connectivity Checks Are Not Just For Design-For-Test Teams


By Pawini Mahajan and Raja Koneru The complexity with system-on-chip (SoC) design continues to grow, creating greater complexity of the corresponding design-for-test (DFT) logic required for manufacturing tests. Design teams are challenged not only by high gate counts and the array of internally developed and third-party IP integrated into their designs: the need to achieve high-quality manu... » read more

The Emergence Of Inline Screening For High Volume Manufacturing


The semiconductor content of automobiles is growing rapidly in applications where quality is of paramount importance, and automotive manufacturers have taken the lead in driving a “Zero Defect” mentality into their supply chain. The motivation behind this paper started with engagements with semiconductor suppliers as well as automotive manufacturers, where KLA witnessed many clear examples ... » read more

Hybrid System-Level Test For RF SiP


In recent years, the proliferation of the IoT has focused attention on low-power-wireless applications. IoT modules incorporating functions such as Bluetooth Low Energy (BLE) transceivers, MCUs, and power-management circuitry are becoming system-in-package (SiP) and even one-chip devices. Such devices increase the demand for a mass-production test environment that can measure them in a short ti... » read more

Characterization Of CMP Processes With White Light Interferometry


Faster computer and electronic processors require smaller features for integrated circuits (IC), which in turn require smaller and smoother substrate surfaces. Chemical mechanical polishing (CMP) has become one of the most critical semiconductor fabrication technologies because it offers a superior means of removing unwanted topography in interlevel dielectric layers and achieving sufficient pl... » read more

In-field, In-Mission Reliability Monitoring Based On Deep Data


This paper describes a Deep Data approach to reliability monitoring in advanced electronics, based on degradation as a precursor for failure. By applying machine learning algorithms and analytics to data created by on-chip monitoring IPs (Agents), IC/system health and performance can be continuously monitored, at all stages of the product lifecycle. Realtime degradation analysis of critical par... » read more

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