Advantages Of Picosecond Ultrasonic Technology For Advanced RF Metrology


This paper is from China Semiconductor Technology International Conference (CSTIC). Picosecond Ultrasonics (PULSE Technology) has been widely adopted as the tool-of-record for metal film thickness metrology in semiconductor fabs around the world. It provides unique advantages, such as being a rapid, non-contact, non-destructive technology, and has capabilities for simultaneous multiple layer... » read more

Finding And Fixing Design And Testbench Coding Errors On The Fly


Two things are certain in chip verification: as many bugs as possible must be found and fixed before fabrication, and this must happen as early as possible in the development process. The much-desired “shift left” in verification requires that advanced analysis and debug technologies be available to engineers from the earliest stages of the project. It is preferable that many classes of err... » read more

ATE In The Age Of Convergence And Exascale Computing


We are currently in the midst of the age of convergence – that is, the convergence of data from a range of applications and data sources. These sources constitute anything that creates data – ranging from human-created data, such as voice and video, through automotive, mobile, and wireless/IoT devices. This also includes edge computing and servers storing the massive amounts of data needed ... » read more

Hunting For Open Defects In Advanced Packages


Catching all defects in chip packaging is becoming more difficult, requiring a mix of electrical tests, metrology screening, and various types of inspection. And the more critical the application for these chips, the greater the effort and the cost. Latent open defects continue to be the bane of test, quality, and reliability engineering. Open defects in packages occur at the chip-to-substra... » read more

Preventing Chips From Burning Up During Test


It’s become increasingly difficult to manage the heat generated during IC test. Absent the proper mitigations, it’s easy to generate so much heat that probe cards and chips literally can burn up. As a result, implementing temperature-management techniques is becoming a critical part of IC testing. “We talk about systems, saying the system is good,” said Arun Krishnamoorthy, senior... » read more

Cloud Vs. On-Premise Analytics


The immense and growing volume of data generated in chip manufacturing is forcing chipmakers to rethink where to process and store that data. For fabs and OSATs, this decision is not one to be taken lightly. The proprietary nature of yield, performance, and other data, and corporate policies to retain tight control of that data, have so far limited outsourcing to the cloud. But as the amount... » read more

Development Of Digital Controlled Technology For High Voltage DC Testing


In recent years, the demand for low power devices has increased due to issues related to global environmental protection. As a result, the demand for high-voltage power devices has also increased. To test such devices, test equipment that can handle high-voltage devices (hereinafter referred to as “test equipment”) is required. In addition, test time must be shortened to reduce manufacturin... » read more

Controlling TC SAW Filter Frequency with Picosecond Ultrasonics


Presented during the poster session at ASMC 2019 PULSE™ technology is a first principles based acoustic metrology technique that is capable of measuring various parameters of interest in semiconductor manufacturing such as multi-layered metal thickness, sound velocity of dielectric films and reflectivity. In this paper, we demonstrate the applications of PULSE technology in the TC-SAW... » read more

Fast Cycle Approximate Simulation Using ARC nSIM NCAM


One of the key factors of successful software (e.g. firmware/application) development is the ability to quickly run and profile software in the absence of target hardware. The earlier in the design process that this is possible, the better, i.e. during the pre-silicon phase. Typically, the pre-silicon phase is dominated by three activities, each with different challenges: Exploring the Ha... » read more

Untangling 3D NAND: Tilt, Registration, And Misalignment


The multiple demands of 3D NAND to enable yield and performance increase in difficulty at each generation. First generation devices, at 24-32 layer pairs, pushed process tools to extremes, going quickly from 10:1 to 40:1 aspect ratios for today’s 64-96 pair single tier devices. The aspect ratios increased as fast as the manufacturing challenges. To continue bit density scaling, processing imp... » read more

← Older posts Newer posts →