New Deep Learning Processors, Embedded FPGA Technologies, SoC Design Solutions


Some of the most valuable events at DAC are the IP Track sessions, which give small and midsize companies a chance to share innovations that might not get much attention elsewhere. The use of IP in SoCs has exploded in recent years. In a panel at DAC 2017, an industry expert noted that the IP market clearly was growing even faster than EDA itself, due to the fact that more and more chip mak... » read more

The Week in Review: IoT


Conferences Internet of Things World 2018 takes place next week at the Santa Clara Convention Center in Silicon Valley. Executives of GE Digital, The Chamberlain Group, and UPS will be among those giving keynote addresses during the four-day conference. Monday will see pre-conference workshops, followed by three days of keynotes, presentations, and an expo floor taking in 100,000 square feet o... » read more

Designing Hardware For Security


By Ed Sperling and Kevin Fogarty Cyber criminals are beginning to target weaknesses in hardware to take control of devices, rather than using the hardware as a stepping stone to access to the software. This shift underscores a significant increase in the sophistication of the attackers, as evidenced by the discovery of Spectre and Meltdown by Google Project Zero in 2017 (made public in Ja... » read more

The Week in Review: IoT


Cybersecurity Arm this week introduced the Cortex-M35P processor with anti-tampering technology and software isolation. The company also debuted security intellectual property to protect Internet of Things devices from physical cyberattacks and close proximity side-channel attacks. Paul Williamson, Arm’s vice president and general manager of the IoT Device IP line of business, provides more ... » read more

Rules Of The Driverless Road


The growing disparity among states, countries and carmakers over autonomous driving is turning what should be a logical progression into chaos. Consider what's happening in California, which is determined to remain the leader in this tech revolution. The state last month relaxed its testing rules so that cars can be monitored remotely, with no driver actually present inside the car. I... » read more

Smart Farming Accelerates


Today I’m taking a brief, but related, detour from my usual automotive blog topics to discuss a bit of what’s happening related to autonomy but in the agricultural industry. This industry carries a market cap of $42.7 billion as a whole for the construction and agricultural machinery market, according to The New York Times, although still smaller than the semiconductor segment, with its ... » read more

Improving Security In Cars


When security researchers first demonstrated that they could hack a car over the internet to control its brakes and transmission, Chrysler had to recall 1.4 million vehicles to fix the software vulnerability. The infamous Jeep hack of 2015 was an expensive wake-up call for the automotive industry. So, what has changed since then? In today’s cars, software now controls everything from safet... » read more

Challenges At The Edge


By Kevin Fogarty and Ed Sperling Edge computing is inching toward the mainstream as the tech industry begins grappling with the fact that far too much data will be generated by sensors to send everything back to the cloud for processing. The initial idea behind the IoT/IIoT, as well as other connected devices, was that simple sensors would relay raw data to the cloud for processing throug... » read more

Tech Talk: HW Security


Ben Levine, senior director of product management at Rambus, explains how to minimize the risk of attacks on chip hardware, why design for security is becoming more critical for connected devices, and strategies for making devices less vulnerable. https://youtu.be/twgHcdqvyjU » read more

Timing Signoff Methodology For eFPGA


An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells. The timing signoff for an eFPGA’s interface with the rest of the chip is designed to leverage standard ASIC timing signoff flow for a hard-macro: as long as inputs/output to/from the eFPGA are all flopped, the int... » read more

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