category: System-Level Design

category: Auto, Security & Edge AI

System Bits: July 16
By Ann Mutschler - 16 Jul, 2018 - Comments: 0

Test tube AI neural network In a significant step towards demonstrating the capacity to program artificial intelligence into synthetic biomolecular circuits, Caltech researchers have developed an artificial neural network made out of DNA that can solve a classic machine learning problem: correctly identifying handwritten numbers. The work was done in the laboratory of Lulu Qian, assistant p... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Jul, 2018 - Comments: 0

M&A Intel will acquire fabless company eASIC. Founded in 1999, eASIC sells structured ASIC platforms that act as a midpoint between FPGAs and standard cell ASICs by combining FPGA-like logic and design flows with single via routing. Eventually, Intel sees potential in using its Embedded Multi-Die Interconnect Bridge (EMIB) technology to combine Intel FPGAs with structured ASICs in a system... » read more

Verification As A Flow (Part 2)
By Brian Bailey - 11 Jul, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

Blog Review: July 11
By Jesse Allen - 11 Jul, 2018 - Comments: 0

Synopsys' Taylor Armerding warns that while significant router vulnerabilities have been known about for years, security mostly hasn't been getting better, leading to a 539% increase in attacks targeting routers since the fourth quarter of 2017. In a video, Mentor's Colin Walls walks through how to deal with the initialization of non-volatile RAM in embedded programming, including suggestion... » read more

System Bits: July 10
By Ann Mutschler - 10 Jul, 2018 - Comments: 0

Foldable electronic switches and sensors Using inexpensive materials, UC Berkeley engineers have created a method to fabricate foldable electronic switches and sensors directly onto paper, along with prototype generators, supercapacitors and other electronic devices for what they said is a range of applications. Besides the fact that it is readily available and low cost, the team pointed ou... » read more

Week In Review: Design, Low Power
By Jesse Allen - 06 Jul, 2018 - Comments: 0

CAST debuted an IP subsystem implementing the latest IEEE standards for Time Sensitive Networking (TSN) over Ethernet. The TSN_CTRL Subsystem combines three IP cores, a time synchronizer, traffic shaper, and Ethernet MAC. It implements a hardware subsystem that operates without software assistance once programmed. The IP communicates timing information to the system, and allows the system to de... » read more

Design Reuse Vs. Abstraction
By Ann Mutschler - 05 Jul, 2018 - Comments: 1

Chip designers have been constantly searching for a hardware description language abstraction level higher than RTL for a few decades. But not everyone is moving in that direction, and there appear to be enough options available through design reuse to forestall that shift for many chipmakers. Pushing to new levels of abstraction is frequent topic of discussion in the design world, particula... » read more

Verification As A Flow (Part 1)
By Brian Bailey - 05 Jul, 2018 - Comments: 2

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

Blog Review: July 4
By Jesse Allen - 04 Jul, 2018 - Comments: 0

Applied Materials' Sundeep Bajikar argues that to get the full benefits of AI, new computing architectures are needed – and that will require new breakthroughs in materials engineering to get beyond classic 2D scaling. Cadence's Tom Wong considers to what extent chip dis-integration is happening and how the industry can cope with the escalating costs of new process nodes and higher-speed i... » read more

System Bits: July 3
By Ann Mutschler - 03 Jul, 2018 - Comments: 0

Machine learning network for personalized autism therapy MIT Media Lab researchers have developed a personalized deep learning network for therapy use with children with autism spectrum conditions. They reminded these children often have trouble recognizing the emotional states of people around them, such as distinguishing a happy face from a fearful face. To help with this, some therapists... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy