Considerations For Accelerating On-Device Stable Diffusion Models


One of the more powerful – and visually stunning – advances in generative AI has been the development of Stable Diffusion models. These models are used for image generation, image denoising, inpainting (reconstructing missing regions in an image), outpainting (generating new pixels that seamlessly extend an image's existing bounds), and bit diffusion. Stable Diffusion uses a type of dif... » read more

Help, 3D-IC Is Stuck In A Country Song


Every time I focus on three-dimensional (3D) integrated circuit (IC) design, I start hearing the Luke Bryan song “Rain Makes Corn, Corn Makes Whiskey.” Not because I need a strong drink to work with 3D-IC designs, but because there is a similar, although slightly more complicated, series of cause and effect issues that impact 3D-ICs. Pushing electrons through very thin metal wires and switc... » read more

A Path To Increase Cell Utilization Rate And Decrease Routing Congestion In Chip Design Floorplanning


What do chip floorplanning and city planning have in common? As it turns out, quite a lot. This was the premise for an award-winning talk given by MediaTek at this year’s Synopsys User Group (SNUG) in Taiwan. Urban city development was used as an example to understand how utilization rate (UR) and congestion relate to chip planning. UR was defined in the example as population density while... » read more

Artificial Intelligence Wonderland


Silicon Catalyst held its Sixth Annual Semiconductor Forum in Menlo Park on the SRI campus on November 9th. Richard Curtin, Managing Partner for Si Catalyst, opened the event with a reference to Arthur C. Clarke’s "2001: A Space Odyssey" and noted how remarkable it was that a novel written back in 1968 was able to foretell the direction of the computer industry over 50 years into the future. ... » read more

SoC Integration And Data Transport Architecture Requirements Surge In 2023


As the holiday season is in full swing, it's retrospection and prediction time! Let's look at what I thought 2023 would look like, review how it turned out, and take a first stab at 2024 predictions. As a spoiler, my biggest surprise was the intensity with which artificial intelligence and machine learning (AI/ML) accelerated since Generative AI was put on the mainstream adoption map last year,... » read more

Successful 3D-IC Design, Verification, And Analysis Requires An Integrated Approach


3D-IC designs enable improvements in performance, power, footprint, and costs that cannot be attained in system-on-chip (SoC) and IC design. However, the leap from traditional SoC/IC design to 3D-IC designs brings not only new opportunities, but also new challenges. Siemens EDA provides multiple 3D-IC design analysis and verification functionalities that address the diverse needs of 3DIC des... » read more

Building Tomorrow’s Electronics Piece By Piece


The semiconductor landscape is undergoing a seismic shift as the demand for more powerful and energy-efficient electronic devices reaches new heights. In a recent panel discussion at CadenceLIVE Europe, featuring luminaries such as Kevork Kechichian from Arm, Paul Cunningham from Cadence, Norbert Schuhmann from Fraunhofer, Trent Uehling from NXP, Davide Rossi from the University of Bologna, an... » read more

Accelerate 5G Testing


The promise of 5G is faster and more reliable communications. To enable mobile broadband communications, 5G uses existing and new technologies to achieve extreme data throughputs. In this white paper, you will learn about the impact of the 3GPP evolution on your testing and solutions available to help you scale to production quickly. Click here to read more. » read more

Blog Review: November 29


Siemens' Matt Walsh checks out electro-thermal design and how a Boundary Condition Independent Reduced Order Model (BCI-ROM) can capture accurate characteristics from a 3D thermal analysis, ready for use in a 1D circuit simulation. Cadence's Vinod Khera considers how EDA could benefit from the AI revolution by providing a productivity boost through virtual assistants and improving code quali... » read more

The Evolution Of RISC-V Processor Verification: Open Standards And Verification IP


The OpenHW Group’s [1] Verification task group has been a pioneer in the development of methodologies and verification collateral for RISC-V processor verification. Since 2019 the members have worked together to develop CORE-V-VERIF: a UVM environment for the verification of RISC-V processor cores. Over this period of time the CORE-V-VERIF environment has evolved as new processor verification... » read more

← Older posts Newer posts →