category: System-Level Design

category: Auto, Security & Edge AI

System Bits: Dec. 12
By Ann Mutschler - 12 Dec, 2017 - Comments: 0

Increasing performance scaling with packageless processors Demand for increasing performance is far outpacing the capability of traditional methods for performance scaling. Disruptive solutions are needed to advance beyond incremental improvements. Traditionally, processors reside inside packages to enable PCB-based integration. However, a team of researchers from the Department of Electrical ... » read more

The Week In Review: Design
By Jesse Allen - 08 Dec, 2017 - Comments: 0

M&A Design services firm Synapse Design acquired the assets of ACEIC Design Technologies, including the engineering team and verification IP. ACEIC, which was based in Bangalore, primarily focused on verification services for wireless 802.11ac MAC IP. This is only the latest expansion move from Synapse. Earlier this year, the company acquired the services companies Tech Vulcan in San Diego... » read more

Blog Review: Dec. 6
By Jesse Allen - 06 Dec, 2017 - Comments: 0

Synopsys' Eric Huang examines electromagnetic interference, the Bit Error Rate in USB 3.2 and how different transfer types handle errors. Mentor's Nitin Bhagwath points out several things that can cause DDR signals to behave badly, from excessive ringing to stubs in the channel. Cadence's Paul McLellan listens in as Oski CEO Vigyan Singhal explains the basics of assertion-based verificati... » read more

Which Verification Engine? (Part 2)
By Ed Sperling - 06 Dec, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

System Bits: Dec. 5
By Ann Mutschler - 05 Dec, 2017 - Comments: 0

[caption id="attachment_429586" align="aligncenter" width="300"] Vivienne Sze, an associate professor of electrical engineering and computer science at MIT. Source: MIT[/caption] Building deep learning hardware A new course at MIT is bringing together both electrical engineering and computer science to educate student in the highly sought after field of deep learning. Vivienne Sze, an assoc... » read more

Good Solutions Create Problems
By Brian Bailey - 04 Dec, 2017 - Comments: 0

I am amazed at the array of products available these days – products that I had no idea existed or needed. And yet, globalization has made it possible for anyone with an idea to get the product made cheaply and can sell it on amazon, even giving it lots of attention by claiming it is worth 10 times the cost to produce and then discounting it 80%. When 3D printing becomes a little more afforda... » read more

UVM Can Kill You. More News At 11
By Neil Johnson - 04 Dec, 2017 - Comments: 0

Ok. I agree. Not a great title. I don’t like it either. Some pretty aggressive clickbait, I know. But it’s got the quick hit, newsy cliffhanger feel that makes you want to tune in anyway, doesn’t it? I had to go for it. For what it’s worth, it wasn’t my first choice. I wanted to go with “What You Don’t Know About UVM Can Kill You. More News at 11”. Same punch. Still the hi... » read more

Big Challenges, Changes For Debug
By Ann Mutschler - 04 Dec, 2017 - Comments: 1

By Ann Steffora Mutschler & Ed Sperling Debugging a chip always has been difficult, but the problem is getting worse at 7nm and 5nm. The number of corner cases is exploding as complexity rises, and some bugs are not even on anyone's radar until well after devices are already in use by end customers. An estimated 39% of verification engineering time is spent on debugging activities the... » read more

Women In Power
By Ann Mutschler - 01 Dec, 2017 - Comments: 0

This is not my usual, technically-focused report, but it's important sometimes to reflect on the human side of the industry, which can seem woefully absent at times in the scramble to get projects out the door and meet quarterly numbers. This past Tuesday, November 28, I moderated a panel of women who are truly inspirational for the achievements in their respective parts of the industry, an... » read more

The Week In Review: Design
By Jesse Allen - 01 Dec, 2017 - Comments: 0

Tools Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors. IP Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup's hardware and software IP works with a CPU or DSP proc... » read more

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