category: Technical Papers

category: Auto, Security & Edge AI

Flexible-Wafer Platform And CMOS-Compatible 300mm Wafer-Scale Integrated-Photonics Fabrication
By Technical Paper Link - 03 Aug, 2024 - Comments: 0

A new technical paper titled "Mechanically-flexible wafer-scale integrated-photonics fabrication platform" was published by researchers at MIT and New York Center for Research, Economic Advancement, Technology, Engineering, and Science (NY CREATES). Abstract "The field of integrated photonics has advanced rapidly due to wafer-scale fabrication, with integrated-photonics platforms and fabric... » read more

Heterogeneity Of 3DICs As A Security Vulnerability
By Technical Paper Link - 01 Aug, 2024 - Comments: 0

A new technical paper titled "Harnessing Heterogeneity for Targeted Attacks on 3-D ICs" was published by Drexel University. Abstract "As 3-D integrated circuits (ICs) increasingly pervade the microelectronics industry, the integration of heterogeneous components presents a unique challenge from a security perspective. To this end, an attack on a victim die of a multi-tiered heterogeneous 3-... » read more

A Hybrid ECO Detailed Placement Flow for Mitigating Dynamic IR Drop (UC San Diego)
By Technical Paper Link - 01 Aug, 2024 - Comments: 0

A new technical paper titled "A Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR Drop" was published by researchers at UC San Diego. Abstract: "With advanced semiconductor technology progressing well into sub-7nm scale, voltage drop has become an increasingly challenging issue. As a result, there has been extensive research focused on predicting and mitigating dynam... » read more

Classification and Localization of Semiconductor Defect Classes in Aggressive Pitches (imec, Screen)
By Technical Paper Link - 01 Aug, 2024 - Comments: 0

A new technical paper titled "An Evaluation of Continual Learning for Advanced Node Semiconductor Defect Inspection" was published by Imec and SCREEN SPE Germany. Abstract "Deep learning-based semiconductor defect inspection has gained traction in recent years, offering a powerful and versatile approach that provides high accuracy, adaptability, and efficiency in detecting and classifying... » read more

Survey of Energy Efficient PIM Processors
By Technical Paper Link - 01 Aug, 2024 - Comments: 0

A new technical paper titled "Survey of Deep Learning Accelerators for Edge and Emerging Computing" was published by researchers at University of Dayton and the Air Force Research Laboratory. Abstract "The unprecedented progress in artificial intelligence (AI), particularly in deep learning algorithms with ubiquitous internet connected smart devices, has created a high demand for AI compu... » read more

Secure Low-Cost In-DRAM Trackers For Mitigating Rowhammer (Georgia Tech, Google, Nvidia)
By Technical Paper Link - 01 Aug, 2024 - Comments: 0

A new technical paper titled "MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker" was published by researchers at Georgia Tech, Google, and Nvidia. Abstract "This paper investigates secure low-cost in-DRAM trackers for mitigating Rowhammer (RH). In-DRAM solutions have the advantage that they can solve the RH problem within the DRAM chip, without relying on other parts of ... » read more

MTJ-Based CRAM Array
By Technical Paper Link - 01 Aug, 2024 - Comments: 0

A new technical paper titled "Experimental demonstration of magnetic tunnel junction-based computational random-access memory" was published by researchers at University of Minnesota and University of Arizona, Tucson. Abstract "The conventional computing paradigm struggles to fulfill the rapidly growing demands from emerging applications, especially those for machine intelligence because ... » read more

Co-optimizing HW Architecture, Memory Footprint, Device Placement And Per-Chip Operator Scheduling (Georgia Tech, Microsoft)
By Technical Paper Link - 28 Jul, 2024 - Comments: 0

A technical paper titled “Integrated Hardware Architecture and Device Placement Search” was published by researchers at Georgia Institute of Technology and Microsoft Research. Abstract: "Distributed execution of deep learning training involves a dynamic interplay between hardware accelerator architecture and device placement strategy. This is the first work to explore the co-optimization ... » read more

CHERI RISC-V: HW Extension for Conditional Capabilities
By Technical Paper Link - 28 Jul, 2024 - Comments: 0

A technical paper titled “Mon CHÈRI <3 Adapting Capability Hardware Enhanced RISC with Conditional Capabilities” was published by researchers at Ericsson Security Research, Université Libre de Bruxelles, and KU Leuven. Abstract: "Up to 10% of memory-safety vulnerabilities in languages like C and C++ stem from uninitialized variables. This work addresses the prevalence and lack of ade... » read more

Using Diffusion Models to Generate Chip Placements (UC Berkeley)
By Technical Paper Link - 27 Jul, 2024 - Comments: 0

A technical paper titled “Chip Placement with Diffusion” was published by researchers at UC Berkeley. Abstract: "Macro placement is a vital step in digital circuit design that defines the physical location of large collections of components, known as macros, on a 2-dimensional chip. The physical layout obtained during placement determines key performance metrics of the chip, such as power... » read more

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