category: Top Stories

category: Auto, Security & Edge AI

The Power Of IP
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler As the number of design starts goes down the corresponding complexity of SoCs has gone up—and continues to grow. Everyone is looking at the value they can bring to the table as increasing proportions of SoCs are either reused from pre-existing IP within the company designing the chip or brought in from outside. Because is economically impractical to start an SoC... » read more

EUV Focus Shifts To Affordability
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By David Lammers Over the past year, key technologists in the semiconductor industry have come around to believing that EUV lithography will be available for critical mask layers in the next three to five years. What is still up for debate is whether EUV will be cost-effective for low-power consumer SoCs. To penetrate that cost-sensitive market, EUV must overcoming hurdles presented by masks, ... » read more

Keeping Models In Sync
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ed Sperling Models and higher levels of abstraction have been hailed as the best choice for developing SoCs at advanced process nodes, but at 28nm and beyond even that approach is showing signs of stress. The number of models needed for a complex SoC has been growing at each new process node, which makes it much more difficult to keep them updated and in sync as the design progresses down t... » read more

Is Asynchronous Technology Ready For Prime Time?
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler As the quest grows to manage power in everything from the handheld smart phone to sensors for automotive applications and contactless payment cards, designers are getting hungry for new design techniques that allow them to hit yield targets within their power budgets. One such design technique is decidedly not new. In fact, the concept of asynchronous techno... » read more

Special Report: Using FPGAs For 3D Stacking
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Xilinx is developing a 3D architecture for its FPGAs and Actel has been approached by SoC makers to use its flash-based FPGA as a layer in a 3D IC stack. Both approaches could radically alter the fundamental equation about the tradeoffs between FPGAs and ASICs—particularly the power and performance overhead normally associated with programmable logic. Xilinx declined to com... » read more

Power Or Performance?
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Pallab Chatterjee Most microprocessors have shifted to new small geometry processes in order to be the most efficient at power and high performance. However there is always a trade-off between power, performance and area (PPA) for semiconductors, and this is especially relevant for processors. In the current design space, processors are created as general-purpose products, but they are gene... » read more

Synopsys To Buy Virage Logic
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Synopsys bought Virage Logic today for $289 million, extending its IP portfolio well beyond just standard I/O and PHY into memory, logic and processor cores. The move strengthens Synopsys’ position as an all-in-one powerhouse with IP that can fit into an integrated flow. “A big part of the value is providing building blocks that work through the SoC flow,” said Joac... » read more

Corners Up, Margins Down
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Complexity, less room for error and concern over adding any extra wires or circuits into chips because it may boost power consumption or affect the thermal profile are making it more difficult to tackle all the corners on an SoC. The problem gets worse with mixed signal chips, where the corners are far less definable. And it gets even more complex when it comes to turning on ... » read more

Changing Opinions About Noise
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Brian Fuller On a sunny, warm May day in 2009, NIST researcher Jason Campbell took the stage at an IEEE event in Austin with a presentation that was sure cast a pall over the booming low-power semiconductor world. Campbell’s paper, written with Liangchun Yu, Kin Cheung, Jin Qin, John S. Suehle, A. Oates, Kuang Sheng, was entitled “Large Random Telegraph Noise in Sub-Threshold Opera... » read more

IP Integration Creates Challenges For Power
By Ed Sperling - 13 May, 2010 - Comments: 0

By Ann Steffora Mutschler Managing power when integrating IP is becoming a critical issue at advanced process nodes—and the problem is getting worse. For starters, static power leakage that occurs when the transistors are “off” gets worse at each node. On top of that, multiple states to minimize dynamic power leakage have pushed complexity even further. Throw in third-party IP from m... » read more

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