Computing Way Outside Of A Box


Mike Muller, CTO of Arm, sat down with Semiconductor Engineering to talk about changing boundaries between client and server machines, the end of Moore's Law and the impact of machine learning on chip architectures. What follows are excerpts of that conversation. SE: Are the lines blurring between what's considered a client device and what's considered a server? Muller: It's less about a ... » read more

The Building Blocks Of Future Compute


Eric Hennenhoefer, vice president of research at Arm, sat down with Semiconductor Engineering to talk about privacy, security, high-performance computing, accelerators, and Arm’s research. What follows are excerpts of that conversation. SE: Privacy, cybersecurity, silicon photonics, quantum computing are all hot topics today. What do you find really interesting with these emerging areas? ... » read more

RISC-V: More Than a Core


The open-source RISC-V instruction set architecture (ISA) is attracting a lot of attention across the semiconductor industry, but its long-term success will depend on levels of cooperation never seen before in the semiconductor industry. The big question now is how committed the industry is to RISC-V's success. The real value that RISC-V brings is the promise of an ecosystem and the opportun... » read more

Power Delivery Affecting Performance At 7nm


Complex interactions and dependencies at 7nm and beyond can create unexpected performance drops in chips that cannot always be caught by signoff tools. This isn't for lack of effort. The amount of time spent trying to determine if an advanced-node chip will work after it is fabricated has been rising steadily for several process nodes. Additional design rules handle everything from variation... » read more

Power Issues Grow For Cloud Chips


Performance levels in traditional or hyperscale data centers are being limited by power and heat caused by an increasing number of processors, memory, disk and operating systems within servers. The problem is so complex and intertwined, though, that solving it requires a series of steps that hopefully add up to a significant reduction across a system. But at 7nm and below, predicting exactly... » read more

Reliability, Machine Learning And Advanced Packaging


Semiconductor Engineering sat down to discuss reliability, resilience, machine learning and advanced packaging with Rahul Goyal, vice president in the technology and manufacturing group at Intel; Rob Aitken, R&D fellow at Arm; John Lee, vice president and general manager of the semiconductor business unit at ANSYS; and Lluis Paris, director of IP portfolio marketing at TSMC. What follows ar... » read more

Cloud Drives Changes In Network Chip Architectures


Cloud data centers have changed the networking topology and how data moves throughout a large data center, prompting significant changes in the architecture of the chips used to route that data and raising a whole new set of design challenges. Cloud computing has emerged as the fast growing segment of the data center market. In fact, it is expected to grow three-fold in the next few years, a... » read more

Aging In Advanced Nodes


Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; Magdy Abadir, vice president of marketing at ... » read more

Enabling Cheaper Design


While the EDA industry tends to focus on cutting edge designs, where design costs are a minor portion of the total cost of product, the electronics industry has a very long tail. The further along the tail you go, the more significant design costs become as a percent of total cost. Many of those designs are traditionally built using standard parts, such as microcontrollers, but as additional... » read more

Process Corner Explosion


The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

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