Machine Learning’s Growing Divide


[getkc id="305" kc_name="Machine learning"] is one of the hottest areas of development, but most of the attention so far has focused on the cloud, algorithms and GPUs. For the semiconductor industry, the real opportunity is in optimizing and packaging solutions into usable forms, such as within the automotive industry or for battery-operated consumer or [getkc id="76" kc_name="IoT"] products. ... » read more

Predictions: Markets And Drivers


Semiconductor Engineering received a record number of predictions this year. Some of them are just wishful thinking, but many are a lot more thoughtful and project what needs to happen for various markets or products to become successful. Those far reaching predictions may not fully happen within 2018, but we give everyone the chance to note the progress made towards their predictions at the en... » read more

Mixed-Signal Issues Worse At 10/7nm


Despite increasingly difficulty in scaling digital logic to 10/7nm, not all designs at the leading edge are digital. In fact, there are mixed-signal components in designs at almost all nodes down to 10/7nm. This may seem surprising because analog scaling has been an issue since about 90nm, but these are not traditional analog components. Analog IP increasingly includes highly integrated, mix... » read more

The Trouble With Models


Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ... » read more

Pushing DRAM’s Limits


If humans ever do create a genuinely self-aware artificial intelligence, it may well exhibit the frustration of waiting for data arrive. The access bandwidth of DRAM-based computer memory has improved by a factor of 20x over the past two decades. Capacity increased 128x during the same period. But latency improved only 1.3x, according to Kevin Chang, a researcher at Carnegie Mellon Universit... » read more

Accounting For Power Earlier


Concerns about power usage in an SoC are far from new, but the adoption of power management techniques still varies by company and by project. Leading semiconductor providers have made the necessary changes in tooling and methodology to account for [getkc id="106" kc_name="power awareness"] because they have to, but the rest of the industry hasn't necessarily caught up. “The companies t... » read more

EDA Challenges Machine Learning


Over the past few years, [getkc id="305" kc_name="machine learning"] (ML) has evolved from an interesting new approach that allows computers to beat champions at chess and Go, into one that is touted as a panacea for almost everything. While there is clearly a lot of hype surrounding this, it appears that machine learning can produce a better outcome for many tasks in the EDA flow than even the... » read more

The Return Of Body Biasing


Body biasing is making a comeback across a wide swath of process nodes as designers wrestle with how to build mobile devices with more functionality and longer battery life. Consider an ultra-low-power IoT device with a wireless sensor, for example, which is meant to last for years without changing a battery. Body biasing can be used to create an ultra-low-leakage sleep state. “In that ... » read more

New Drivers For I/O


Interface standards are on a tear, and new markets are pushing the standards in several directions at the same time. The result could be a lot more innovation and some updates in areas that looked to be well established. Traditionally, this has been a sleepy and predictable part of the industry with standards bodies producing updates to their interfaces at a reasonable rate. Getting data int... » read more

Lots Of Little Knobs For Power


Dynamic power is becoming a much bigger worry at new nodes as more finFETs are packed on a die and wires shrink to the point where resistance and capacitance become first-order effects. Chipmakers began seeing dynamic power density issues with the first generation of [getkc id="185" kc_name="finFETs"]. While the 3D transistor structures reduced leakage current by providing better gate contro... » read more

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