category: Top Stories

category: Auto, Security & Edge AI

Power Gating And Power-Centric Programing
By Ed Sperling - 03 Nov, 2011 - Comments: 0

By Pallab Chatterjee SoC design has a number of techniques for power management. One of the more prevalent methods is to use power gating to turn on and off blocks based on applications being run, and mode controls. Power gating while being supported by the two major EDA power design flows, UPF and CPF, still has some implementation challenges. The flows have to make sure that the states of... » read more

Limits For TSVs In 3D Stacks?
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling Semiconductor design always has been about solving technology issues one node at a time, often in the face of a perpetual barrage of looming problems. In fact, if there is any change at all, it’s in the number of threats that have to be solved now at each node, most of them driven by ever-increasing density and the laws of physics. Stacking die holds the promise of becoming... » read more

Redefining Systems Around Power
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling Engineers have been talking about system-level power budgets since Moore’s Law reached 65nm, but as power becomes a critical element of any design with or without a plug the definition of what constitutes a system is changing. While most SoC engineers think of the system as an IC, power increasingly is playing a significant role in the subsystem, and even in the larger syst... » read more

Low Power Drives Performance And TCO
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Pallab Chatterjee A common theme at this year’s Custom Integrated Circuit Conference was the reduction of power and power management while increasing data throughput. Historically, the show has featured new techniques for ultra high accuracy and brute force improvements in performance at all costs. The main theme this year was that in a world of mobile endpoint devices, the goal is to get... » read more

Thermal Modeling Held Back By Outdated Standards
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler As the reality of true 3D IC design nears, engineering teams are keen to manage the heat between the stacked die in order to avoid catastrophic failures. Thermal modeling tops the roster of techniques to leverage in this area. Herve Jaouen, director of modeling and simulation in STMicroelectronics’ technology R&D organization, explained that in 3D designs the... » read more

Energy Vs. Power
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler The terms power and energy are used almost interchangeably these days, but understanding and clearly articulating how to optimize embedded designs for maximum energy and power efficiency can make a big difference in a design. At a physics level, energy = power x time, whereas power is the rate of energy in a given time window. When the focus is specifically power, ... » read more

The Hidden Costs Of Test
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling As complexity grows in SoCs, so does the ability to accurately test them. That helps explain why there are so many different types of tests and so much confusion about what to use to perform those tests, when to test, and where in the flows to include those tests. But what’s less well known is that tests done improperly also can give false results, labeling good chips as bad�... » read more

DFT: Essential For Power-Aware Test
By Ed Sperling - 18 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler Power-aware test is a major manufacturing consideration due to the problems of increased power dissipation in various test modes, as well as test implications that come up with the usage of various low-power design technologies. Challenges for test engineers and test tool developers include understanding the various concerns associated with power-aware test, develo... » read more

TSVs Ease Heat In 3D ICs
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler In the evolving discussion of 3D ICs and through silicon via (TSV) technology, a key issue engineering teams are facing today is how to reduce the thermal coefficients between substrates in a stacked die. Simply put, what is the best way to get the heat out of the 2.5 or 3D IC? The answer, of course, is anything but simple. “In a 3D system, the heat hierarchy ... » read more

Solar Designs Focus On Low Power
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Pallab Chatterjee This year’s Semicon West showed growth in both attendees and exhibitors, but the big growth—at least from a percentage standpoint—was in the associated Intersolar show, which featured advances in PV and solar thermal systems. This year’s Intersolar show covered areas that were not just commercial grid-tied PV systems. Rather, it also had off-grid systems with ne... » read more

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