category: Top Stories

category: Auto, Security & Edge AI

Heat Wreaks Havoc
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler As semiconductor manufacturing technology has scaled ever smaller, the density of power grid networks has caused on-chip temperatures to rise, negatively impacting performance, power, and reliability. CMOS technology, still the predominant material in SoCs, was originally conceived as a low-power technology when compared with the bipolar approach, which was a very... » read more

Low Power Drives New Architectures
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Pallab Chatterjee Power became the driving discussion at several major events last month. The global cries for energy reduction, which have been mainstream since the early 1970s on the political level, have now moved to being real economic realities for component and systems suppliers. Chipmakers are finding that lower power makes good economic sense—lower cost of packaging, lower cost... » read more

More Analog Needed For Multicore SoCs
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Mike Demler Minimizing on-chip power consumption continues to be one of the greatest challenges facing SoC designers. Everyone who owns a cell phone has undoubtedly seen the effect on limited battery life firsthand, but the impact on the unseen compute servers in “the cloud” is even more severe, making total electrical operating costs greater than the hardware expense, according to AMD ... » read more

Customer Perspective: STMicroelectronics
By Ed Sperling - 11 Aug, 2011 - Comments: 0

By Ed Sperling Philippe Magarshack, group vice president for technology R&D at STMicroelectronics, sat down with Low-Power Engineering to talk about some of the fundamental changes ahead in how SoCs are designed, built, how they perform and what steps can be taken to speed time to market. LPE: What do you see as the biggest changes ahead? Magarshack: One is the sheer size of the ecosy... » read more

Getting The Balance Right
By Ann Mutschler - 11 Aug, 2011 - Comments: 0

Defining the power architecture for a low-power design means striking a balance between the high-level abstraction and measurements made typically at RTL and below, but today that is easier said than done. “The balance is that at the high level of abstraction, the design choices you make have a big effect over power, yet your ability to measure them is incomplete until you get much further... » read more

Dueling Power Formats
By Ed Sperling - 11 Aug, 2011 - Comments: 0

By Ed Sperling Multiple power formats and increasingly complex SoCs don’t sound like a winning formula. So just how bad have things become? Low-Power Engineering asked Sorin Dobre, senior staff engineer at Qualcomm, for a real-world assessment of the situation. LPE: There are three power formats—CPF, UPF and IEEE 1801. How big a problem is this for Qualcomm? Dobre: Actually we have CPF... » read more

Apache Update: Five Important Questions
By Ed Sperling - 11 Aug, 2011 - Comments: 0

By Ed Sperling It was supposed to be the first IPO since Magma went public in 2001. Instead, Apache was bought by Ansys in a deal that closed earlier this month—at a record pace for the EDA industry of less than two months since it was announced. So what exactly was behind the acquisition and why did Apache agree to sell? And what will become of Apache within the much larger Ansys? Low... » read more

Extending Battery Life
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ed Sperling In the past it was all about clock frequency. People bought the latest computer and frequently paid a premium because it could crunch numbers faster. But as computing moves from the desktop into handheld devices, that focus is radically changing. Low-Power Engineering caught up with Mark Bohr, senior fellow and director of Intel’s process architecture and integration, to ta... » read more

Low Power: Coming To A CE Device Near You
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Pallab Chatterjee Low power and connectivity are the two pervasive design constraints for chips and systems being designed today, and they are showing up in devices that have not had architectural changes in decades. Some of the changes are customer-driven, some are consortia-driven, and international cooperation is making some of the regulatory-driven. The regulatory side is moving slow... » read more

Design For Power Methodology
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Steffora Mutschler It is rare to find an advanced chip today that has not been designed considering power from the very earliest point. In fact, it is safe to say that power is the No. 1 priority, or a close No. 2. But to achieve the highest performance for a low-power design, a design-for-power methodology is necessary, comprised of the capabilities to implement power in the most ef... » read more

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