category: Top Stories

category: Auto, Security & Edge AI

The Growing Confidence Gap In Verification
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ed Sperling It’s no surprise that verification is getting more difficult at each new process node. What’s less obvious is just how deep into organizations the job of verifying SoCs and ASICs now extends. Functional verification used to be a well-defined job at the back end of the design flow. It has evolved into a multi-dimensional, multi-group challenge, beginning at the earliest st... » read more

Calculating Emulation’s Complex Cost Of Ownership
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Hardware emulation or hardware-assisted verification –whichever term you choose—has been around for decades. But until recently it has seen only modest adoption due to the high cost, long set-up time, power and IT requirements, among other things. But with simulation running out of steam between 50 and 100 million gates, this specialized hardware makes a ... » read more

Quantum Shifts
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ed Sperling Intel, STMicroelectronics and some of the leading memory providers already are working on 10nm process technology, and advanced researchers in universities and industry-leading companies are looking at 7nm, 5nm and even beyond. Those who have glimpsed this technological future have similar observations. There is no single technology problem that has to be solved at these node... » read more

Executive Briefing: Aart de Geus
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler EDA, IP, semiconductors, electronics…actually every industry is woven into the tapestry of a global macroeconomic system. Running a business successfully within this environment requires a unique skillset; at once entrepreneurial as well as wise and discerning. System-Level Design sat down with Aart de Geus, chairman and co-CEO of Synopsys, to discuss these iss... » read more

Thanks For The Memories
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The amount of real estate in a design now devoted to memories—SRAM on chip, DRAM off chip, and a few other more exotic options showing up occasionally—is a testament to the amount of data that needs to be utilized quickly in both mobile and fixed devices. Memory is almost singlehandedly responsible for the routing congestion now plaguing complex SoCs. It is one of the mai... » read more

Where Does It Hurt?
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The IC design industry is feeling a new kind of pain—this one driven by uncertainty over architectural shifts, new ecosystem interactions and new ways to account for costs. As mainstream ICs move from 50/45/40nm to around 32/28/22nm, there are only two choices for design teams—continue shrinking features or stack dies. In many cases, the ultimate solution may be a combina... » read more

Like Oil And Water
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler For years, the promise and allure of a concurrent design methodology included talk of models, high-level synthesis, virtual prototyping and other system-level technologies all peacefully coexisting in a single design methodology. While it sounds like a good idea, the model-based design approach hasn’t mixed well with the virtual prototype approach. And at l... » read more

The Good And Bad Of Models
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by fierce competition and the fact that socket decisions are made long before silicon is manufactured, semiconductor companies today ship models and virtual prototypes to their OEMs very early in hopes of locking in the socket. Admittedly, this has been happening for some time, but due to complexity and the need for flexibility of models and virtual platf... » read more

Inflection Points Ahead
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Engineering challenges have existed at every process node in semiconductor designs, but at 20nm and beyond, engineers and executives on all sides of the industry are talking about inflection points. An inflection point is literally the place where a curve on a graph turns down or up, but in the semiconductor industry it’s usually associated with the point at which a progres... » read more

Dealing With Test More Effectively
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Shrinking geometries are starting to have the same effect on test as they are on other parts of an SoC, with the focus shifting from area to leakage, heat, noise, signal integrity, and the impact on overall system performance. The warning that design teams have to consider test much earlier in the design was issued to chipmakers years ago and largely ignored. At 28nm that war... » read more

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