Designs Getting Squeezed


It's taking longer to get chips manufactured these days. At advanced nodes, there are more steps on the photomask side as a result of double and multi-patterning. And at established nodes, an explosion in demand for chips aimed at automotive and [getkc id="76" comment="Internet of Things"]—particularly on the industrial IoT side ([getkc id="78" kc_name="IIoT"])—has created demand-driven con... » read more

What Is Functional Accuracy?


What it means to be functionally accurate in the context of [getkc id="104" kc_name="virtual platforms"] varies greatly, depending upon whom you ask and even when you ask them. But that doesn’t mean that functional accuracy isn’t useful. Jon McDonald, technical marketing engineer for the design and creation business at [getentity id="22017" e_name="Mentor Graphics"], expects to see a lot... » read more

Is SystemC Broken?


In order to perform architectural exploration, performance analysis and optimization, early validation of software, improved productivity in hardware development and many other tasks, the industry needs a viable [getkc id="104" kc_name="virtual prototype"]. That requires a suitable language in order to express necessary concepts at a high enough level of [getkc id="101" kc_name="abstraction"] s... » read more

Design By Architect Or Committee?


Everything we do is based on a language. It doesn’t matter if we are talking about design, verification, specification, software or mask data. They all provide a way to communicate intent, and then there are engines that work on the intent to produce something else that is desirable, also based on a language. Over time, the EDA industry has built up a hierarchy of languages from the most deta... » read more

Ecosystem Changes


Semiconductor Engineering sat down to discuss changes in the semiconductor ecosystem with Kelvin Low, senior director of foundry marketing at [getentity id="22865" e_name="Samsung Semiconductor"]; John Costello, vice president of product planning at [getentity id="22849" e_name="Altera"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"], and Michiel Ligthart, p... » read more

First Time Success And Cost Control


First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

Mentor Graphics Buys Tanner EDA


By Ed Sperling & Brian Bailey [getentity id="22017" e_name="Mentor Graphics"] has just purchased [getentity id="22561" e_name="Tanner EDA"] for an undisclosed sum, according to sources close to the deal. The acquisition moves Mentor squarely into the analog and mixed signal tools world, while positioning it to play a much bigger role in the Internet of Things market. Mentor isn't t... » read more

Partition Lines Growing Fuzzy


For as long as most semiconductor engineers can remember, chips with discrete functions started out on a printed circuit board, progressed into chip sets when it made sense and eventually were integrated onto the same die. The primary motivations behind this trend were performance and cost—shorter distance, fewer mask layers, less silicon. But this equation has been changing over the past ... » read more

Incremental Design Methodologies


There are times when we become stuck in the past, or choose to believe something that is no longer true or actually never was true. As we get older, we are all guilty of that. History tends to rewrite itself, especially given that this industry is aging. One of these situations occurred recently, and comments from an industry luminary didn’t align with the thoughts and memories of other peopl... » read more

IP Market Booms At Advanced Nodes


As [getkc id="81" kc_name="SoC"] design and manufacturing costs rise, system OEMs are wringing as much of that increase as they can from ASIC vendors. The result is that engineering teams on the design and test side are being constrained by budgets at a time when complexity is rising and time-to-market pressures are increasing. At least one segment is benefiting from directly this. Budgetary... » read more

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