Dealing With Deadlocks


Deadlocks are becoming increasingly problematic as designs becoming more complex and heterogeneous. Rather than just integrating IP, the challenge is understanding all of the possible interactions and dependencies. That affects the choice of IP, how it is implemented in a design, and how it is verified. And it adds a whole bunch of unknowns into an already complex formula for return on inves... » read more

Toward Neuromorphic Designs


Part one of this series considered the mechanisms of learning and memory in biological brains. Each neuron has many fibers, which connect to adjacent neurons at synapses. The concentration of ions such as potassium and calcium inside the cell is different from the concentration outside. The cellular membrane thus serves as a capacitor. When a stimulus is received, the neuron releases neur... » read more

Radar Versus LiDAR


Demand is picking up for vision, radar and LiDAR sensors that enable assisted and autonomous driving capabilities in cars, but carmakers are now pushing for some new and demanding requirements from suppliers. The automotive market always has been tough on suppliers. OEMs want smaller, faster and cheaper devices at the same or improved safety levels for both advanced driver-assistance systems... » read more

Searching For EUV Mask Defects


Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this technology can be used in production. One lingering issue that is becoming more worrisome is how to find [gettech id="31045" comment="EUV"] mask defects. That isn't the only issue, of course. The industry continues to work on the power source and resists. Bu... » read more

MEMS Market Shifting


The MEMS sector is beginning to look more promising, bolstered by new end-market demand and different packaging options that require more advanced engineering, processes and new materials. All of this points to higher selling prices, which are long overdue in this space. For years, the market for microelectromechanical systems was populated by too many companies vying for too few opportunit... » read more

Next-Gen Mask Writer Race Begins


Competition is heating up in the mask writer equipment business as two vendors—Intel/IMS and NuFlare—vie for position in the new and emerging multi-beam tool segment. Last year, Intel surprised the industry by acquiring IMS Nanofabrication, a multi-beam e-beam mask writer equipment vendor. Also last year, IMS, now part of Intel, began shipping the world’s first multi-beam mask writer f... » read more

Memory Test Challenges, Opportunities


The semiconductor capital equipment market is on fire, and the memory chip test equipment sector is no different. But it is getting much more difficult on the memory side. Memory test vendors are contending with next-generation devices, such as 3D NAND flash memories, HBM2 chips, low-power double-data-rate DRAMs, graphics DRAMs, phase-change memories, magnetoresistive RAMs, and resistive RAM... » read more

How To Build An IoT Chip (Part 2)


Semiconductor Engineering sat down to discuss IoT chip design issues with Jeff Miller, product marketing manager for electronic design systems in the Deep Submicron Division of [getentity id="22017" e_name="Mentor, a Siemens Business"]; Mike Eftimakis, IoT product manager in [getentity id="22186" e_name="Arm"]'s Systems and Software Group; and John Tinson, vice president of sales at Sondrel Ltd... » read more

Targeting And Tailoring eFPGAs


Robert Blake, president and CEO of Achronix, sat down with Semiconductor Engineering to discuss what's changing in the embedded FPGA world, why new levels of customization are so important, and difficulty levels for implementing embedded programmability. What follows are excerpts of that discussion. SE: There are numerous ways you can go about creating a chip these days, but many of the prot... » read more

New Power Concerns At 10/7nm


As chip sizes and complexity continues to grow exponentially at 7nm and below, managing power is becoming much more difficult. There are a number of factors that come into play at advanced nodes, including more and different types of processors, more chip-package decisions, and more susceptibility to noise of all sorts due to thinner insulation layers and wires. The result is that engineers ... » read more

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